0.2 v 8T SRAM with improved bitline sensing using column-based data randomization

Anh Tuan Do; Zhaochuan Lee; Bo Wang; Ik Joon Chang; Tony T. Kim

doi:10.1109/ASSCC.2014.7008880

0.2 v 8T SRAM with improved bitline sensing using column-based data randomization

Anh Tuan Do
, Zhaochuan Lee
, Bo Wang
, Ik Joon Chang
, Tony T. Kim

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Citation (Scopus)

Abstract

8T SRAMs operating at sub-threshold supply voltages suffer from bit-line swing degradation when the data pattern of a column is dominated by '1' or '0'. Worst case scenarios happen when the accessed bit is different from the rest of the column. In this work, a simplified Linear Feedback Shift Register (LFSR) is used to shuffle input data so that distribution of '1' and '0' in each column is close to 50%. As a result, bit-line sensing margin is enhanced. In addition, a bitline boost biasing scheme is applied to further increase the bitline swing and the sensing window. A 16Kb test chips fabricated in a 65 nm CMOS technology demonstrates successful SRAM operation at 0.2 V, room temperate, having power consumption and access time of 0.7 μW and 2.5 μs, respectively.

Original language	English
Title of host publication	2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	141-144
Number of pages	4
ISBN (Electronic)	9781479940905
DOIs	https://doi.org/10.1109/ASSCC.2014.7008880
Publication status	Published - 13 Jan 2015
Event	2014 10th IEEE Asian Solid-State Circuits Conference, A-SSCC 2014 - Kaohsiung, Taiwan, Province of China Duration: 10 Nov 2014 → 12 Nov 2014

Publication series

Name	2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers

Conference

Conference	2014 10th IEEE Asian Solid-State Circuits Conference, A-SSCC 2014
Country/Territory	Taiwan, Province of China
City	Kaohsiung
Period	10/11/14 → 12/11/14

Bibliographical note

Publisher Copyright:
© 2014 IEEE.

Access to Document

10.1109/ASSCC.2014.7008880

Cite this

Do, A. T., Lee, Z., Wang, B., Chang, I. J., & Kim, T. T. (2015). 0.2 v 8T SRAM with improved bitline sensing using column-based data randomization. In 2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers (pp. 141-144). Article 7008880 (2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASSCC.2014.7008880

Do, Anh Tuan ; Lee, Zhaochuan ; Wang, Bo et al. / 0.2 v 8T SRAM with improved bitline sensing using column-based data randomization. 2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2015. pp. 141-144 (2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers).

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title = "0.2 v 8T SRAM with improved bitline sensing using column-based data randomization",

abstract = "8T SRAMs operating at sub-threshold supply voltages suffer from bit-line swing degradation when the data pattern of a column is dominated by '1' or '0'. Worst case scenarios happen when the accessed bit is different from the rest of the column. In this work, a simplified Linear Feedback Shift Register (LFSR) is used to shuffle input data so that distribution of '1' and '0' in each column is close to 50\%. As a result, bit-line sensing margin is enhanced. In addition, a bitline boost biasing scheme is applied to further increase the bitline swing and the sensing window. A 16Kb test chips fabricated in a 65 nm CMOS technology demonstrates successful SRAM operation at 0.2 V, room temperate, having power consumption and access time of 0.7 μW and 2.5 μs, respectively.",

author = "Do, \{Anh Tuan\} and Zhaochuan Lee and Bo Wang and Chang, \{Ik Joon\} and Kim, \{Tony T.\}",

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doi = "10.1109/ASSCC.2014.7008880",

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Do, AT, Lee, Z, Wang, B, Chang, IJ & Kim, TT 2015, 0.2 v 8T SRAM with improved bitline sensing using column-based data randomization. in 2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers., 7008880, 2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers, Institute of Electrical and Electronics Engineers Inc., pp. 141-144, 2014 10th IEEE Asian Solid-State Circuits Conference, A-SSCC 2014, Kaohsiung, Taiwan, Province of China, 10/11/14. https://doi.org/10.1109/ASSCC.2014.7008880

0.2 v 8T SRAM with improved bitline sensing using column-based data randomization. / Do, Anh Tuan; Lee, Zhaochuan; Wang, Bo et al.
2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2015. p. 141-144 7008880 (2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - 0.2 v 8T SRAM with improved bitline sensing using column-based data randomization

AU - Do, Anh Tuan

AU - Lee, Zhaochuan

AU - Wang, Bo

AU - Chang, Ik Joon

AU - Kim, Tony T.

PY - 2015/1/13

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N2 - 8T SRAMs operating at sub-threshold supply voltages suffer from bit-line swing degradation when the data pattern of a column is dominated by '1' or '0'. Worst case scenarios happen when the accessed bit is different from the rest of the column. In this work, a simplified Linear Feedback Shift Register (LFSR) is used to shuffle input data so that distribution of '1' and '0' in each column is close to 50%. As a result, bit-line sensing margin is enhanced. In addition, a bitline boost biasing scheme is applied to further increase the bitline swing and the sensing window. A 16Kb test chips fabricated in a 65 nm CMOS technology demonstrates successful SRAM operation at 0.2 V, room temperate, having power consumption and access time of 0.7 μW and 2.5 μs, respectively.

AB - 8T SRAMs operating at sub-threshold supply voltages suffer from bit-line swing degradation when the data pattern of a column is dominated by '1' or '0'. Worst case scenarios happen when the accessed bit is different from the rest of the column. In this work, a simplified Linear Feedback Shift Register (LFSR) is used to shuffle input data so that distribution of '1' and '0' in each column is close to 50%. As a result, bit-line sensing margin is enhanced. In addition, a bitline boost biasing scheme is applied to further increase the bitline swing and the sensing window. A 16Kb test chips fabricated in a 65 nm CMOS technology demonstrates successful SRAM operation at 0.2 V, room temperate, having power consumption and access time of 0.7 μW and 2.5 μs, respectively.

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Do AT, Lee Z, Wang B, Chang IJ, Kim TT. 0.2 v 8T SRAM with improved bitline sensing using column-based data randomization. In 2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers. Institute of Electrical and Electronics Engineers Inc. 2015. p. 141-144. 7008880. (2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers). doi: 10.1109/ASSCC.2014.7008880

0.2 v 8T SRAM with improved bitline sensing using column-based data randomization

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