Abstract
The proposed Δ -based spike sorting (SS) SoC is the first on-chip implementation of an analog computing-in-memory (CIM) binary autoencoder neural network (B-AENN) feature extraction with enhanced spike detection adopting Δ -spikes, resulting in the highest on-chip SS classification accuracy of 94.54%. It also allows to reduce the digital data transmission rate by 48.8× compared to prior SS systems.
| Original language | English |
|---|---|
| Title of host publication | 2024 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2024 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| ISBN (Electronic) | 9798350361469 |
| DOIs | |
| Publication status | Published - 2024 |
| Event | 2024 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2024 - Honolulu, United States Duration: 16 Jun 2024 → 20 Jun 2024 |
Publication series
| Name | Digest of Technical Papers - Symposium on VLSI Technology |
|---|---|
| ISSN (Print) | 0743-1562 |
Conference
| Conference | 2024 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2024 |
|---|---|
| Country/Territory | United States |
| City | Honolulu |
| Period | 16/06/24 → 20/06/24 |
Bibliographical note
Publisher Copyright:© 2024 IEEE.
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