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A Δ-Based Spike Sorting SoC with End-to-End Implementation of Event-Driven Binary Autoencoder Neural Network in Analog CIM Achieving 94.54% Accuracy and 3.11μW/ch

  • Edward Choi
  • , Vincent Lukito
  • , Injun Choi
  • , Seoyoung Lee
  • , Ik Joon Chang
  • , Sohmyung Ha
  • , Minkyu Je

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Citations (Scopus)

Abstract

The proposed Δ -based spike sorting (SS) SoC is the first on-chip implementation of an analog computing-in-memory (CIM) binary autoencoder neural network (B-AENN) feature extraction with enhanced spike detection adopting Δ -spikes, resulting in the highest on-chip SS classification accuracy of 94.54%. It also allows to reduce the digital data transmission rate by 48.8× compared to prior SS systems.

Original languageEnglish
Title of host publication2024 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2024
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9798350361469
DOIs
Publication statusPublished - 2024
Event2024 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2024 - Honolulu, United States
Duration: 16 Jun 202420 Jun 2024

Publication series

NameDigest of Technical Papers - Symposium on VLSI Technology
ISSN (Print)0743-1562

Conference

Conference2024 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2024
Country/TerritoryUnited States
CityHonolulu
Period16/06/2420/06/24

Bibliographical note

Publisher Copyright:
© 2024 IEEE.

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