A 16 GB 1024 GB/s HBM3 DRAM with On-Die Error Control Scheme for Enhanced RAS Features

Yesin Ryu; Young Cheon Kwon; Jae Hoon Lee; Sung Gi Ahn; Jaewon Park; Kijun Lee; Yu Ho Choi; Han Won Cho; Jae San Kim; Jungyu Lee; Haesuk Lee; Seung Ho Song; Je Min Ryu; Yeong Ho Yun; Useung Shin; Dajung Cho; Jeong Hoan Park; Jae Seung Jeong; Sukhan Lee; Kyoung Hwan Lim; Tae Sung Kim; Kyungmin Kim; Yu Jin Cha; Ik Joo Lee; Tae Kyu Byun; Han Sik Yoo; Yeong Geol Song; Myung Kyu Lee; Sunghye Cho; Sung Rae Kim; Ji Min Choi; Hyoung Min Kim; Soo Young Kim; Jaeyoun Youn; Myeong O. Kim; Kyomin Sohn; Sang Joon Hwang; Joo Young Lee

doi:10.1109/VLSITechnologyandCir46769.2022.9830391

A 16 GB 1024 GB/s HBM3 DRAM with On-Die Error Control Scheme for Enhanced RAS Features

Yesin Ryu, Young Cheon Kwon, Jae Hoon Lee, Sung Gi Ahn, Jaewon Park, Kijun Lee, Yu Ho Choi, Han Won Cho, Jae San Kim, Jungyu Lee, Haesuk Lee, Seung Ho Song, Je Min Ryu, Yeong Ho Yun, Useung Shin, Dajung Cho, Jeong Hoan Park, Jae Seung Jeong, Sukhan Lee, Kyoung Hwan LimTae Sung Kim, Kyungmin Kim, Yu Jin Cha, Ik Joo Lee, Tae Kyu Byun, Han Sik Yoo, Yeong Geol Song, Myung Kyu Lee, Sunghye Cho, Sung Rae Kim, Ji Min Choi, Hyoung Min Kim, Soo Young Kim, Jaeyoun Youn, Myeong O. Kim, Kyomin Sohn, Sang Joon Hwang, Joo Young Lee

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

6 Citations (Scopus)

Abstract

This paper presents the symbol-based On-die ECC (OD-ECC) configuration of High Bandwidth Memory-3 (HBM3) to correct a 16-bit error, bounded by a sub-wordline (WL), and implementation for parallelized data bus inversion (DBI). In addition, the die-to-die integration method for error check and scrub (ECS) mode, and programmable memory built-in self-test (MBIST) design approach for at-speed test are de-scribed. The fabricated HBM3 improves the error detection rate by 92.2% with 99.7% fault coverage of OD-ECC logic while achieving 8.0 Gb/s/pin.

Original language	English
Title of host publication	2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	130-131
Number of pages	2
ISBN (Electronic)	9781665497725
DOIs	https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830391
Publication status	Published - 2022
Event	2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022 - Honolulu, United States Duration: 12 Jun 2022 → 17 Jun 2022

Publication series

Name	Digest of Technical Papers - Symposium on VLSI Technology
Volume	2022-June
ISSN (Print)	0743-1562

Conference

Conference	2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022
Country/Territory	United States
City	Honolulu
Period	12/06/22 → 17/06/22

Bibliographical note

Publisher Copyright:
© 2022 IEEE.

Keywords

DRAM
ECC
ECS
HBM3
MBIST
RAS

Access to Document

10.1109/VLSITechnologyandCir46769.2022.9830391

Cite this

Ryu, Y., Kwon, Y. C., Lee, J. H., Ahn, S. G., Park, J., Lee, K., Choi, Y. H., Cho, H. W., Kim, J. S., Lee, J., Lee, H., Song, S. H., Min Ryu, J., Yun, Y. H., Shin, U., Cho, D., Park, J. H., Jeong, J. S., Lee, S., ... Lee, J. Y. (2022). A 16 GB 1024 GB/s HBM3 DRAM with On-Die Error Control Scheme for Enhanced RAS Features. In 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022 (pp. 130-131). (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2022-June). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830391

@inproceedings{eef680424a054cce846a191fbe1b3542,

title = "A 16 GB 1024 GB/s HBM3 DRAM with On-Die Error Control Scheme for Enhanced RAS Features",

abstract = "This paper presents the symbol-based On-die ECC (OD-ECC) configuration of High Bandwidth Memory-3 (HBM3) to correct a 16-bit error, bounded by a sub-wordline (WL), and implementation for parallelized data bus inversion (DBI). In addition, the die-to-die integration method for error check and scrub (ECS) mode, and programmable memory built-in self-test (MBIST) design approach for at-speed test are de-scribed. The fabricated HBM3 improves the error detection rate by 92.2% with 99.7% fault coverage of OD-ECC logic while achieving 8.0 Gb/s/pin.",

keywords = "DRAM, ECC, ECS, HBM3, MBIST, RAS",

author = "Yesin Ryu and Kwon, {Young Cheon} and Lee, {Jae Hoon} and Ahn, {Sung Gi} and Jaewon Park and Kijun Lee and Choi, {Yu Ho} and Cho, {Han Won} and Kim, {Jae San} and Jungyu Lee and Haesuk Lee and Song, {Seung Ho} and {Min Ryu}, Je and Yun, {Yeong Ho} and Useung Shin and Dajung Cho and Park, {Jeong Hoan} and Jeong, {Jae Seung} and Sukhan Lee and Lim, {Kyoung Hwan} and Kim, {Tae Sung} and Kyungmin Kim and Cha, {Yu Jin} and {Joo Lee}, Ik and Byun, {Tae Kyu} and {Sik Yoo}, Han and Song, {Yeong Geol} and Lee, {Myung Kyu} and Sunghye Cho and Kim, {Sung Rae} and Choi, {Ji Min} and Kim, {Hyoung Min} and {Young Kim}, Soo and Jaeyoun Youn and Kim, {Myeong O.} and Kyomin Sohn and Hwang, {Sang Joon} and Lee, {Joo Young}",

note = "Publisher Copyright: {\textcopyright} 2022 IEEE.; 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022 ; Conference date: 12-06-2022 Through 17-06-2022",

year = "2022",

doi = "10.1109/VLSITechnologyandCir46769.2022.9830391",

language = "English",

series = "Digest of Technical Papers - Symposium on VLSI Technology",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "130--131",

booktitle = "2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022",

address = "United States",

}

Ryu, Y, Kwon, YC, Lee, JH, Ahn, SG, Park, J, Lee, K, Choi, YH, Cho, HW, Kim, JS, Lee, J, Lee, H, Song, SH, Min Ryu, J, Yun, YH, Shin, U, Cho, D, Park, JH, Jeong, JS, Lee, S, Lim, KH, Kim, TS, Kim, K, Cha, YJ, Joo Lee, I, Byun, TK, Sik Yoo, H, Song, YG, Lee, MK, Cho, S, Kim, SR, Choi, JM, Kim, HM, Young Kim, S, Youn, J, Kim, MO, Sohn, K, Hwang, SJ & Lee, JY 2022, A 16 GB 1024 GB/s HBM3 DRAM with On-Die Error Control Scheme for Enhanced RAS Features. in 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022. Digest of Technical Papers - Symposium on VLSI Technology, vol. 2022-June, Institute of Electrical and Electronics Engineers Inc., pp. 130-131, 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022, Honolulu, United States, 12/06/22. https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830391

A 16 GB 1024 GB/s HBM3 DRAM with On-Die Error Control Scheme for Enhanced RAS Features. / Ryu, Yesin; Kwon, Young Cheon; Lee, Jae Hoon et al.
2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022. Institute of Electrical and Electronics Engineers Inc., 2022. p. 130-131 (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2022-June).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Ryu, Yesin

AU - Kwon, Young Cheon

AU - Lee, Jae Hoon

AU - Ahn, Sung Gi

AU - Park, Jaewon

AU - Lee, Kijun

AU - Choi, Yu Ho

AU - Cho, Han Won

AU - Kim, Jae San

AU - Lee, Jungyu

AU - Lee, Haesuk

AU - Song, Seung Ho

AU - Min Ryu, Je

AU - Yun, Yeong Ho

AU - Shin, Useung

AU - Cho, Dajung

AU - Park, Jeong Hoan

AU - Jeong, Jae Seung

AU - Lee, Sukhan

AU - Lim, Kyoung Hwan

AU - Kim, Tae Sung

AU - Kim, Kyungmin

AU - Cha, Yu Jin

AU - Joo Lee, Ik

AU - Byun, Tae Kyu

AU - Sik Yoo, Han

AU - Song, Yeong Geol

AU - Lee, Myung Kyu

AU - Cho, Sunghye

AU - Kim, Sung Rae

AU - Choi, Ji Min

AU - Kim, Hyoung Min

AU - Young Kim, Soo

AU - Youn, Jaeyoun

AU - Kim, Myeong O.

AU - Sohn, Kyomin

AU - Hwang, Sang Joon

AU - Lee, Joo Young

PY - 2022

Y1 - 2022

N2 - This paper presents the symbol-based On-die ECC (OD-ECC) configuration of High Bandwidth Memory-3 (HBM3) to correct a 16-bit error, bounded by a sub-wordline (WL), and implementation for parallelized data bus inversion (DBI). In addition, the die-to-die integration method for error check and scrub (ECS) mode, and programmable memory built-in self-test (MBIST) design approach for at-speed test are de-scribed. The fabricated HBM3 improves the error detection rate by 92.2% with 99.7% fault coverage of OD-ECC logic while achieving 8.0 Gb/s/pin.

AB - This paper presents the symbol-based On-die ECC (OD-ECC) configuration of High Bandwidth Memory-3 (HBM3) to correct a 16-bit error, bounded by a sub-wordline (WL), and implementation for parallelized data bus inversion (DBI). In addition, the die-to-die integration method for error check and scrub (ECS) mode, and programmable memory built-in self-test (MBIST) design approach for at-speed test are de-scribed. The fabricated HBM3 improves the error detection rate by 92.2% with 99.7% fault coverage of OD-ECC logic while achieving 8.0 Gb/s/pin.

KW - DRAM

KW - ECC

KW - ECS

KW - HBM3

KW - MBIST

KW - RAS

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U2 - 10.1109/VLSITechnologyandCir46769.2022.9830391

DO - 10.1109/VLSITechnologyandCir46769.2022.9830391

M3 - Conference contribution

AN - SCOPUS:85135211899

T3 - Digest of Technical Papers - Symposium on VLSI Technology

SP - 130

EP - 131

BT - 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022

Y2 - 12 June 2022 through 17 June 2022

ER -

Ryu Y, Kwon YC, Lee JH, Ahn SG, Park J, Lee K et al. A 16 GB 1024 GB/s HBM3 DRAM with On-Die Error Control Scheme for Enhanced RAS Features. In 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022. Institute of Electrical and Electronics Engineers Inc. 2022. p. 130-131. (Digest of Technical Papers - Symposium on VLSI Technology). doi: 10.1109/VLSITechnologyandCir46769.2022.9830391

A 16 GB 1024 GB/s HBM3 DRAM with On-Die Error Control Scheme for Enhanced RAS Features

Abstract

Publication series

Conference

Bibliographical note

Keywords

Access to Document

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