A Low jitter, Fast recoverable, Fully analog DLL using Tracking ADC For High Speed and Low Stand-by power DDR I/O interface

Se Jun Kim; Sang Hoon Hong; Jae Kyung Wee; Jin Hong Ahn; Jin Yong Chung

doi:10.1109/VLSIC.2003.1221228

A Low jitter, Fast recoverable, Fully analog DLL using Tracking ADC For High Speed and Low Stand-by power DDR I/O interface

Se Jun Kim
, Sang Hoon Hong
, Jae Kyung Wee
, Jin Hong Ahn
, Jin Yong Chung

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

4 Citations (Scopus)

Abstract

For high bandwidth and low stand-by power DDR (Double Data Rate) I/O interface, a new fully analog DLL (Delay Locked Loop) are designed and implemented in 0.16μm DRAM process. Utilizing a tracking ADC (Analog-to-Digital Converter), a large stand-by current of the analog DLL is suppressed without losing locking information nor compromising jitter performance. Two-step duty correction scheme using multiphase clocks and phase mixing corrects an inherent duty-error of a system clock with more precision and speed, especially for a large duty-error. Proposed DLL has a 100MHz-520MHz wide lock-range and a 65psec peak-to-peak jitter and 0.064psec/mv supply sensitivity at 2.3v supply voltage consuming 1.1mA of stand-by current.

Original language	English
Title of host publication	2003 Symposium on VLSI Circuits, VLSIC 2003 - Digest of Technical Papers
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	285-286
Number of pages	2
ISBN (Print)	4891140348
DOIs	https://doi.org/10.1109/VLSIC.2003.1221228
Publication status	Published - 2003
Event	2003 Symposium on VLSI Circuits, VLSIC 2003 - Kyoto, Japan Duration: 12 Jun 2003 → 14 Jun 2003

Publication series

Name	IEEE Symposium on VLSI Circuits, Digest of Technical Papers
ISSN (Print)	2158-5601
ISSN (Electronic)	2158-5636

Conference

Conference	2003 Symposium on VLSI Circuits, VLSIC 2003
Country/Territory	Japan
City	Kyoto
Period	12/06/03 → 14/06/03

Access to Document

10.1109/VLSIC.2003.1221228

Cite this

Kim, S. J., Hong, S. H., Wee, J. K., Ahn, J. H., & Chung, J. Y. (2003). A Low jitter, Fast recoverable, Fully analog DLL using Tracking ADC For High Speed and Low Stand-by power DDR I/O interface. In 2003 Symposium on VLSI Circuits, VLSIC 2003 - Digest of Technical Papers (pp. 285-286). (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSIC.2003.1221228

Kim, Se Jun ; Hong, Sang Hoon ; Wee, Jae Kyung et al. / A Low jitter, Fast recoverable, Fully analog DLL using Tracking ADC For High Speed and Low Stand-by power DDR I/O interface. 2003 Symposium on VLSI Circuits, VLSIC 2003 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2003. pp. 285-286 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

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title = "A Low jitter, Fast recoverable, Fully analog DLL using Tracking ADC For High Speed and Low Stand-by power DDR I/O interface",

abstract = "For high bandwidth and low stand-by power DDR (Double Data Rate) I/O interface, a new fully analog DLL (Delay Locked Loop) are designed and implemented in 0.16μm DRAM process. Utilizing a tracking ADC (Analog-to-Digital Converter), a large stand-by current of the analog DLL is suppressed without losing locking information nor compromising jitter performance. Two-step duty correction scheme using multiphase clocks and phase mixing corrects an inherent duty-error of a system clock with more precision and speed, especially for a large duty-error. Proposed DLL has a 100MHz-520MHz wide lock-range and a 65psec peak-to-peak jitter and 0.064psec/mv supply sensitivity at 2.3v supply voltage consuming 1.1mA of stand-by current.",

author = "Kim, \{Se Jun\} and Hong, \{Sang Hoon\} and Wee, \{Jae Kyung\} and Ahn, \{Jin Hong\} and Chung, \{Jin Yong\}",

year = "2003",

doi = "10.1109/VLSIC.2003.1221228",

language = "English",

isbn = "4891140348",

series = "IEEE Symposium on VLSI Circuits, Digest of Technical Papers",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "285--286",

booktitle = "2003 Symposium on VLSI Circuits, VLSIC 2003 - Digest of Technical Papers",

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note = "2003 Symposium on VLSI Circuits, VLSIC 2003 ; Conference date: 12-06-2003 Through 14-06-2003",

}

Kim, SJ, Hong, SH, Wee, JK, Ahn, JH & Chung, JY 2003, A Low jitter, Fast recoverable, Fully analog DLL using Tracking ADC For High Speed and Low Stand-by power DDR I/O interface. in 2003 Symposium on VLSI Circuits, VLSIC 2003 - Digest of Technical Papers. IEEE Symposium on VLSI Circuits, Digest of Technical Papers, Institute of Electrical and Electronics Engineers Inc., pp. 285-286, 2003 Symposium on VLSI Circuits, VLSIC 2003, Kyoto, Japan, 12/06/03. https://doi.org/10.1109/VLSIC.2003.1221228

A Low jitter, Fast recoverable, Fully analog DLL using Tracking ADC For High Speed and Low Stand-by power DDR I/O interface. / Kim, Se Jun; Hong, Sang Hoon; Wee, Jae Kyung et al.
2003 Symposium on VLSI Circuits, VLSIC 2003 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2003. p. 285-286 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Chung, Jin Yong

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N2 - For high bandwidth and low stand-by power DDR (Double Data Rate) I/O interface, a new fully analog DLL (Delay Locked Loop) are designed and implemented in 0.16μm DRAM process. Utilizing a tracking ADC (Analog-to-Digital Converter), a large stand-by current of the analog DLL is suppressed without losing locking information nor compromising jitter performance. Two-step duty correction scheme using multiphase clocks and phase mixing corrects an inherent duty-error of a system clock with more precision and speed, especially for a large duty-error. Proposed DLL has a 100MHz-520MHz wide lock-range and a 65psec peak-to-peak jitter and 0.064psec/mv supply sensitivity at 2.3v supply voltage consuming 1.1mA of stand-by current.

AB - For high bandwidth and low stand-by power DDR (Double Data Rate) I/O interface, a new fully analog DLL (Delay Locked Loop) are designed and implemented in 0.16μm DRAM process. Utilizing a tracking ADC (Analog-to-Digital Converter), a large stand-by current of the analog DLL is suppressed without losing locking information nor compromising jitter performance. Two-step duty correction scheme using multiphase clocks and phase mixing corrects an inherent duty-error of a system clock with more precision and speed, especially for a large duty-error. Proposed DLL has a 100MHz-520MHz wide lock-range and a 65psec peak-to-peak jitter and 0.064psec/mv supply sensitivity at 2.3v supply voltage consuming 1.1mA of stand-by current.

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Kim SJ, Hong SH, Wee JK, Ahn JH, Chung JY. A Low jitter, Fast recoverable, Fully analog DLL using Tracking ADC For High Speed and Low Stand-by power DDR I/O interface. In 2003 Symposium on VLSI Circuits, VLSIC 2003 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc. 2003. p. 285-286. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). doi: 10.1109/VLSIC.2003.1221228

A Low jitter, Fast recoverable, Fully analog DLL using Tracking ADC For High Speed and Low Stand-by power DDR I/O interface

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