A low power 128Mb pseudo SRAM using hyper destructive read architecture

Jin Hong Ahn; Sang Hoon Hong; Jae Bum Ko; Se Jun Kim; Sung Won Shin; Hee Bok Kang; Jae Jin Lee; Joong Sik Kih

doi:10.1109/ASSCC.2005.251678

A low power 128Mb pseudo SRAM using hyper destructive read architecture

Jin Hong Ahn
, Sang Hoon Hong
, Jae Bum Ko
, Se Jun Kim
, Sung Won Shin
, Hee Bok Kang
, Jae Jin Lee
, Joong Sik Kih

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Citation (Scopus)

Abstract

A 128Mb Pseudo SRAM is developed using a special type of architecture with the purpose of effectively reducing the standby current. Standby current, especially the off leakage current is becoming more difficult problem to handle in modern devices because shorter channel length in high density and high speed devices are at a point where off leakage is the major source. In order to solve this issue, Hyper Destructive Read Architecture (HyDRA) is developed. HyDRA is a special DRAM architecture enabling destructive reading of DRAM cells using global bitline and extra tag memory. The paper demonstrates HyDRA utilizing its fast row cycle capability to instead minimize standby power to 150uA @ 2.1V and 90°C while maintaining the speed and chip area of the conventional scheme using the same process technology.

Original language	English
Title of host publication	2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005
Publisher	IEEE Computer Society
Pages	113-116
Number of pages	4
ISBN (Print)	0780391624, 9780780391628
DOIs	https://doi.org/10.1109/ASSCC.2005.251678
Publication status	Published - 2005
Event	1st IEEE Asian Solid-State Circuits Conference, ASSCC 2005 - Hsinchu, Taiwan, Province of China Duration: 1 Nov 2005 → 3 Nov 2005

Publication series

Name	2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005

Conference

Conference	1st IEEE Asian Solid-State Circuits Conference, ASSCC 2005
Country/Territory	Taiwan, Province of China
City	Hsinchu
Period	1/11/05 → 3/11/05

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10.1109/ASSCC.2005.251678

Cite this

Ahn, J. H., Hong, S. H., Ko, J. B., Kim, S. J., Shin, S. W., Kang, H. B., Lee, J. J., & Kih, J. S. (2005). A low power 128Mb pseudo SRAM using hyper destructive read architecture. In 2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005 (pp. 113-116). Article 4017544 (2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005). IEEE Computer Society. https://doi.org/10.1109/ASSCC.2005.251678

@inproceedings{5eb469c9e3c74db586e3d0163777cf6d,

title = "A low power 128Mb pseudo SRAM using hyper destructive read architecture",

abstract = "A 128Mb Pseudo SRAM is developed using a special type of architecture with the purpose of effectively reducing the standby current. Standby current, especially the off leakage current is becoming more difficult problem to handle in modern devices because shorter channel length in high density and high speed devices are at a point where off leakage is the major source. In order to solve this issue, Hyper Destructive Read Architecture (HyDRA) is developed. HyDRA is a special DRAM architecture enabling destructive reading of DRAM cells using global bitline and extra tag memory. The paper demonstrates HyDRA utilizing its fast row cycle capability to instead minimize standby power to 150uA @ 2.1V and 90°C while maintaining the speed and chip area of the conventional scheme using the same process technology.",

author = "Ahn, \{Jin Hong\} and Hong, \{Sang Hoon\} and Ko, \{Jae Bum\} and Kim, \{Se Jun\} and Shin, \{Sung Won\} and Kang, \{Hee Bok\} and Lee, \{Jae Jin\} and Kih, \{Joong Sik\}",

year = "2005",

doi = "10.1109/ASSCC.2005.251678",

language = "English",

isbn = "0780391624",

series = "2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005",

publisher = "IEEE Computer Society",

pages = "113--116",

booktitle = "2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005",

address = "United States",

}

Ahn, JH, Hong, SH, Ko, JB, Kim, SJ, Shin, SW, Kang, HB, Lee, JJ & Kih, JS 2005, A low power 128Mb pseudo SRAM using hyper destructive read architecture. in 2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005., 4017544, 2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005, IEEE Computer Society, pp. 113-116, 1st IEEE Asian Solid-State Circuits Conference, ASSCC 2005, Hsinchu, Taiwan, Province of China, 1/11/05. https://doi.org/10.1109/ASSCC.2005.251678

A low power 128Mb pseudo SRAM using hyper destructive read architecture. / Ahn, Jin Hong; Hong, Sang Hoon; Ko, Jae Bum et al.
2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005. IEEE Computer Society, 2005. p. 113-116 4017544 (2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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T1 - A low power 128Mb pseudo SRAM using hyper destructive read architecture

AU - Ahn, Jin Hong

AU - Hong, Sang Hoon

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AU - Kim, Se Jun

AU - Shin, Sung Won

AU - Kang, Hee Bok

AU - Lee, Jae Jin

AU - Kih, Joong Sik

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N2 - A 128Mb Pseudo SRAM is developed using a special type of architecture with the purpose of effectively reducing the standby current. Standby current, especially the off leakage current is becoming more difficult problem to handle in modern devices because shorter channel length in high density and high speed devices are at a point where off leakage is the major source. In order to solve this issue, Hyper Destructive Read Architecture (HyDRA) is developed. HyDRA is a special DRAM architecture enabling destructive reading of DRAM cells using global bitline and extra tag memory. The paper demonstrates HyDRA utilizing its fast row cycle capability to instead minimize standby power to 150uA @ 2.1V and 90°C while maintaining the speed and chip area of the conventional scheme using the same process technology.

AB - A 128Mb Pseudo SRAM is developed using a special type of architecture with the purpose of effectively reducing the standby current. Standby current, especially the off leakage current is becoming more difficult problem to handle in modern devices because shorter channel length in high density and high speed devices are at a point where off leakage is the major source. In order to solve this issue, Hyper Destructive Read Architecture (HyDRA) is developed. HyDRA is a special DRAM architecture enabling destructive reading of DRAM cells using global bitline and extra tag memory. The paper demonstrates HyDRA utilizing its fast row cycle capability to instead minimize standby power to 150uA @ 2.1V and 90°C while maintaining the speed and chip area of the conventional scheme using the same process technology.

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Y2 - 1 November 2005 through 3 November 2005

ER -

A low power 128Mb pseudo SRAM using hyper destructive read architecture

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