A low power two-step cyclic time-to-digital converter without startup time error in 180 nm CMOS

Van Nhan Nguyen; Jong Wook Lee

doi:10.1109/SIGTELCOM.2018.8325773

A low power two-step cyclic time-to-digital converter without startup time error in 180 nm CMOS

Van Nhan Nguyen
, Jong Wook Lee

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Citations (Scopus)

Abstract

We present a low power, small area time-to-digital converter (TDC) based on Venier cyclic digital controlled oscillator (DCO) structure. The TDC is designed to be combined with an array of single photon avalanche diodes (SPAD) arranged in a digital silicon photomultiplier (SiPM) architecture to form a fluorescence lifetime sensor. The high dynamic range is achieved by using two individual counters in two (coarse and fine) conversion steps. The TDC is fabricated in 0.18 μm CMOS process in a compact chip area of 0.23 × 0.12 mm². Using a 1.8 V supply, the TDC achieves a resolution of 100 ps, dynamic range of 160 ns and an average power consumption of 0.8 mW.

Original language	English
Title of host publication	Proceedings - 2018 2nd International Conference on Recent Advances in Signal Processing, Telecommunications and Computing, SIGTELCOM 2018
Editors	Vo Nguyen Quoc Bao, Tran Trung Duy
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	116-120
Number of pages	5
ISBN (Electronic)	9781538629765
DOIs	https://doi.org/10.1109/SIGTELCOM.2018.8325773
Publication status	Published - 26 Mar 2018
Event	2nd International Conference on Recent Advances in Signal Processing, Telecommunications and Computing, SIGTELCOM 2018 - Ho Chi Minh City, Viet Nam Duration: 29 Jan 2018 → 31 Jan 2018

Publication series

Name	Proceedings - 2018 2nd International Conference on Recent Advances in Signal Processing, Telecommunications and Computing, SIGTELCOM 2018
Volume	2018-January

Conference

Conference	2nd International Conference on Recent Advances in Signal Processing, Telecommunications and Computing, SIGTELCOM 2018
Country/Territory	Viet Nam
City	Ho Chi Minh City
Period	29/01/18 → 31/01/18

Bibliographical note

Publisher Copyright:
© 2018 IEEE.

Keywords

CMOS
Time to digital converter (TDC)
biomedical imaging

Access to Document

10.1109/SIGTELCOM.2018.8325773

Cite this

Nguyen, V. N., & Lee, J. W. (2018). A low power two-step cyclic time-to-digital converter without startup time error in 180 nm CMOS. In V. N. Q. Bao, & T. T. Duy (Eds.), Proceedings - 2018 2nd International Conference on Recent Advances in Signal Processing, Telecommunications and Computing, SIGTELCOM 2018 (pp. 116-120). (Proceedings - 2018 2nd International Conference on Recent Advances in Signal Processing, Telecommunications and Computing, SIGTELCOM 2018; Vol. 2018-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/SIGTELCOM.2018.8325773

Nguyen, Van Nhan ; Lee, Jong Wook. / A low power two-step cyclic time-to-digital converter without startup time error in 180 nm CMOS. Proceedings - 2018 2nd International Conference on Recent Advances in Signal Processing, Telecommunications and Computing, SIGTELCOM 2018. editor / Vo Nguyen Quoc Bao ; Tran Trung Duy. Institute of Electrical and Electronics Engineers Inc., 2018. pp. 116-120 (Proceedings - 2018 2nd International Conference on Recent Advances in Signal Processing, Telecommunications and Computing, SIGTELCOM 2018).

@inproceedings{6db6066a78944005b2efa5adaeee5fa4,

title = "A low power two-step cyclic time-to-digital converter without startup time error in 180 nm CMOS",

abstract = "We present a low power, small area time-to-digital converter (TDC) based on Venier cyclic digital controlled oscillator (DCO) structure. The TDC is designed to be combined with an array of single photon avalanche diodes (SPAD) arranged in a digital silicon photomultiplier (SiPM) architecture to form a fluorescence lifetime sensor. The high dynamic range is achieved by using two individual counters in two (coarse and fine) conversion steps. The TDC is fabricated in 0.18 μm CMOS process in a compact chip area of 0.23 × 0.12 mm2. Using a 1.8 V supply, the TDC achieves a resolution of 100 ps, dynamic range of 160 ns and an average power consumption of 0.8 mW.",

keywords = "CMOS, Time to digital converter (TDC), biomedical imaging",

author = "Nguyen, \{Van Nhan\} and Lee, \{Jong Wook\}",

note = "Publisher Copyright: {\textcopyright} 2018 IEEE.; 2nd International Conference on Recent Advances in Signal Processing, Telecommunications and Computing, SIGTELCOM 2018 ; Conference date: 29-01-2018 Through 31-01-2018",

year = "2018",

month = mar,

day = "26",

doi = "10.1109/SIGTELCOM.2018.8325773",

language = "English",

series = "Proceedings - 2018 2nd International Conference on Recent Advances in Signal Processing, Telecommunications and Computing, SIGTELCOM 2018",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "116--120",

editor = "Bao, \{Vo Nguyen Quoc\} and Duy, \{Tran Trung\}",

booktitle = "Proceedings - 2018 2nd International Conference on Recent Advances in Signal Processing, Telecommunications and Computing, SIGTELCOM 2018",

address = "United States",

}

Nguyen, VN & Lee, JW 2018, A low power two-step cyclic time-to-digital converter without startup time error in 180 nm CMOS. in VNQ Bao & TT Duy (eds), Proceedings - 2018 2nd International Conference on Recent Advances in Signal Processing, Telecommunications and Computing, SIGTELCOM 2018. Proceedings - 2018 2nd International Conference on Recent Advances in Signal Processing, Telecommunications and Computing, SIGTELCOM 2018, vol. 2018-January, Institute of Electrical and Electronics Engineers Inc., pp. 116-120, 2nd International Conference on Recent Advances in Signal Processing, Telecommunications and Computing, SIGTELCOM 2018, Ho Chi Minh City, Viet Nam, 29/01/18. https://doi.org/10.1109/SIGTELCOM.2018.8325773

A low power two-step cyclic time-to-digital converter without startup time error in 180 nm CMOS. / Nguyen, Van Nhan; Lee, Jong Wook.
Proceedings - 2018 2nd International Conference on Recent Advances in Signal Processing, Telecommunications and Computing, SIGTELCOM 2018. ed. / Vo Nguyen Quoc Bao; Tran Trung Duy. Institute of Electrical and Electronics Engineers Inc., 2018. p. 116-120 (Proceedings - 2018 2nd International Conference on Recent Advances in Signal Processing, Telecommunications and Computing, SIGTELCOM 2018; Vol. 2018-January).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A low power two-step cyclic time-to-digital converter without startup time error in 180 nm CMOS

AU - Nguyen, Van Nhan

AU - Lee, Jong Wook

PY - 2018/3/26

Y1 - 2018/3/26

N2 - We present a low power, small area time-to-digital converter (TDC) based on Venier cyclic digital controlled oscillator (DCO) structure. The TDC is designed to be combined with an array of single photon avalanche diodes (SPAD) arranged in a digital silicon photomultiplier (SiPM) architecture to form a fluorescence lifetime sensor. The high dynamic range is achieved by using two individual counters in two (coarse and fine) conversion steps. The TDC is fabricated in 0.18 μm CMOS process in a compact chip area of 0.23 × 0.12 mm2. Using a 1.8 V supply, the TDC achieves a resolution of 100 ps, dynamic range of 160 ns and an average power consumption of 0.8 mW.

AB - We present a low power, small area time-to-digital converter (TDC) based on Venier cyclic digital controlled oscillator (DCO) structure. The TDC is designed to be combined with an array of single photon avalanche diodes (SPAD) arranged in a digital silicon photomultiplier (SiPM) architecture to form a fluorescence lifetime sensor. The high dynamic range is achieved by using two individual counters in two (coarse and fine) conversion steps. The TDC is fabricated in 0.18 μm CMOS process in a compact chip area of 0.23 × 0.12 mm2. Using a 1.8 V supply, the TDC achieves a resolution of 100 ps, dynamic range of 160 ns and an average power consumption of 0.8 mW.

KW - CMOS

KW - Time to digital converter (TDC)

KW - biomedical imaging

UR - https://www.scopus.com/pages/publications/85047875841

U2 - 10.1109/SIGTELCOM.2018.8325773

DO - 10.1109/SIGTELCOM.2018.8325773

M3 - Conference contribution

AN - SCOPUS:85047875841

T3 - Proceedings - 2018 2nd International Conference on Recent Advances in Signal Processing, Telecommunications and Computing, SIGTELCOM 2018

SP - 116

EP - 120

BT - Proceedings - 2018 2nd International Conference on Recent Advances in Signal Processing, Telecommunications and Computing, SIGTELCOM 2018

A2 - Bao, Vo Nguyen Quoc

A2 - Duy, Tran Trung

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2nd International Conference on Recent Advances in Signal Processing, Telecommunications and Computing, SIGTELCOM 2018

Y2 - 29 January 2018 through 31 January 2018

ER -

Nguyen VN, Lee JW. A low power two-step cyclic time-to-digital converter without startup time error in 180 nm CMOS. In Bao VNQ, Duy TT, editors, Proceedings - 2018 2nd International Conference on Recent Advances in Signal Processing, Telecommunications and Computing, SIGTELCOM 2018. Institute of Electrical and Electronics Engineers Inc. 2018. p. 116-120. (Proceedings - 2018 2nd International Conference on Recent Advances in Signal Processing, Telecommunications and Computing, SIGTELCOM 2018). doi: 10.1109/SIGTELCOM.2018.8325773

A low power two-step cyclic time-to-digital converter without startup time error in 180 nm CMOS

Abstract

Publication series

Conference

Bibliographical note

Keywords

Access to Document

Other files and links

Fingerprint

Cite this