Areal Geometric Effects of a ZnO Charge-Trap Layer on Memory Transistor Operations for Embedded-Memory Circuit Applications

The areal geometric effects of a ZnO charge-trap layer (CTL) on the device characteristics of a charge-trap memory thin-film transistor were investigated for embedded-memory circuit applications. While the device with a larger overlapped region between the CTL and active channel exhibited a larger memory window and faster program speed, in order to guarantee long-term memory retention even under higher drain bias conditions, the CTL size should be minimized to reduce the overlapped area. The resulting device behavior is a compromise between the modulations of the number of trap sites within the ZnO CTL and the electric field concentration caused by the configuration of the edge area in the overlapped region.