Compact wide bandwidth dual-port DRAM architecture suitable for mobile multimedia processors

A DRAM architecture capable of providing dual-port interface is presented. The architecture utilises a novel global bitline scheme to obtain a very wide data bandwidth not possible using traditional DRAM architectures. Furthermore, the area penalty is minimised by using a conventional one-transistor one-capacitor cell coupled with special sensing units that have 84.6 more transistor count. The architecture allows simultaneous read and write access using a conventional two-metal DRAM fabrication process.