Design and Technology Co-Optimization for Useful Skew Scheduling on Multi-Bit Flip-Flops

Utilizing multi-bit flip-flops (MBFFs) in circuit implementation offers a considerable saving on the dynamic power dissipated at the clock networks. However, indiscreetly allocating MBFFs by grouping single-bit flip-flops at the logic synthesis or placement stage in order to maximally save dynamic power severely hinders a full applicability of useful clock skew scheduling to the individual flip-flops in MBFFs, failing in effectively optimizing circuit timing. This is because the two internal clock inverters, consequently, the clock skew value, in an MBFF are shared by all of the flip-flops in the MBFF. This work overcomes this inherent limitation of inflexibility in MBFFs for useful clock skew scheduling by proposing a comprehensive DTCO (design and technology co-optimization) framework integrating two viable techniques, called in-place MBFF debanking and skew driven cell layout diversification. Precisely, we proposed a two-step DTCO flow: (1) DTCO based on in-place MBFF debanking technique at the pre-route stage to facilitate the full applicability of useful skew scheduling at the subsequent stages and (2) DTCO utilizing MBFF cell layout diversification technique at the post-route stage, by which useful clock skew scheduling can effectively resolve timing violations. Through experiments with OpenCores benchmark circuits, it is shown that our proposed DTCO flow of reinforcing the effectiveness of useful clock skew scheduling on circuits with MBFF instances is able to reduce the worst and total negative slacks by 16.87% and 46.26% at the cost of 1.00% power overhead over that produced by the state-of-the-art conventional flow.