Device Feasibility of 60-nm-Scaled Vertical-Channel Memory Transistors Using InGaZnO Channel and ZnO Charge-Trap Layers

Yun Ju Cho; Young Ha Kwon; Nak Jin Seong; Kyu Jeong Choi; Hee Ok Kim; Jong Heon Yang; Chi Sun Hwang; Sung Min Yoon

doi:10.1109/TED.2024.3350562

Device Feasibility of 60-nm-Scaled Vertical-Channel Memory Transistors Using InGaZnO Channel and ZnO Charge-Trap Layers

Yun Ju Cho, Young Ha Kwon, Nak Jin Seong, Kyu Jeong Choi, Hee Ok Kim, Jong Heon Yang, Chi Sun Hwang, Sung Min Yoon

Research output: Contribution to journal › Article › peer-review

4 Citations (Scopus)

Abstract

A 60-nm channel length vertical-channel charge-trap memory (V-CTM) using oxide semiconductor channel was demonstrated for advanced memory applications. Mesa-type vertical channel was well implemented to reduce cell footprint as well as vertical distance. The fabricated V-CTM exhibited a memory window (MW) of 7.7 V between the program and erase states with simple incremental step-pulse programming (ISPP) scheme, verifying the facile erase capability of the designed V-CTM. There was not any marked degradation in device parameters with scaling the channel length from 300 to 60 nm. Long retention time (>108 s) and robust endurance (>104 cycles) were also secured. Four-level multistates could be assigned with ISPP.

Original language	English
Pages (from-to)	1839-1844
Number of pages	6
Journal	IEEE Transactions on Electron Devices
Volume	71
Issue number	3
DOIs	https://doi.org/10.1109/TED.2024.3350562
Publication status	Published - 1 Mar 2024

Bibliographical note

Publisher Copyright:
© 1963-2012 IEEE.

Keywords

Atomic-layer deposition (ALD)
ZnO charge trap layer
charge trap memory
oxide semiconductor
thin film transistor
vertical channel structure

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10.1109/TED.2024.3350562

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title = "Device Feasibility of 60-nm-Scaled Vertical-Channel Memory Transistors Using InGaZnO Channel and ZnO Charge-Trap Layers",

abstract = "A 60-nm channel length vertical-channel charge-trap memory (V-CTM) using oxide semiconductor channel was demonstrated for advanced memory applications. Mesa-type vertical channel was well implemented to reduce cell footprint as well as vertical distance. The fabricated V-CTM exhibited a memory window (MW) of 7.7 V between the program and erase states with simple incremental step-pulse programming (ISPP) scheme, verifying the facile erase capability of the designed V-CTM. There was not any marked degradation in device parameters with scaling the channel length from 300 to 60 nm. Long retention time (>108 s) and robust endurance (>104 cycles) were also secured. Four-level multistates could be assigned with ISPP.",

keywords = "Atomic-layer deposition (ALD), ZnO charge trap layer, charge trap memory, oxide semiconductor, thin film transistor, vertical channel structure",

author = "Cho, {Yun Ju} and Kwon, {Young Ha} and Seong, {Nak Jin} and Choi, {Kyu Jeong} and Kim, {Hee Ok} and Yang, {Jong Heon} and Hwang, {Chi Sun} and Yoon, {Sung Min}",

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AU - Cho, Yun Ju

AU - Kwon, Young Ha

AU - Seong, Nak Jin

AU - Choi, Kyu Jeong

AU - Kim, Hee Ok

AU - Yang, Jong Heon

AU - Hwang, Chi Sun

AU - Yoon, Sung Min

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N2 - A 60-nm channel length vertical-channel charge-trap memory (V-CTM) using oxide semiconductor channel was demonstrated for advanced memory applications. Mesa-type vertical channel was well implemented to reduce cell footprint as well as vertical distance. The fabricated V-CTM exhibited a memory window (MW) of 7.7 V between the program and erase states with simple incremental step-pulse programming (ISPP) scheme, verifying the facile erase capability of the designed V-CTM. There was not any marked degradation in device parameters with scaling the channel length from 300 to 60 nm. Long retention time (>108 s) and robust endurance (>104 cycles) were also secured. Four-level multistates could be assigned with ISPP.

AB - A 60-nm channel length vertical-channel charge-trap memory (V-CTM) using oxide semiconductor channel was demonstrated for advanced memory applications. Mesa-type vertical channel was well implemented to reduce cell footprint as well as vertical distance. The fabricated V-CTM exhibited a memory window (MW) of 7.7 V between the program and erase states with simple incremental step-pulse programming (ISPP) scheme, verifying the facile erase capability of the designed V-CTM. There was not any marked degradation in device parameters with scaling the channel length from 300 to 60 nm. Long retention time (>108 s) and robust endurance (>104 cycles) were also secured. Four-level multistates could be assigned with ISPP.

KW - Atomic-layer deposition (ALD)

KW - ZnO charge trap layer

KW - charge trap memory

KW - oxide semiconductor

KW - thin film transistor

KW - vertical channel structure

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Device Feasibility of 60-nm-Scaled Vertical-Channel Memory Transistors Using InGaZnO Channel and ZnO Charge-Trap Layers

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Keywords

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