Effect of the Blocking Oxide Layer with Asymmetric Taper Angles in 3-D NAND Flash Memories

Jun Gyu Lee; Woo Je Jung; Jae Hyeon Park; Keon Ho Yoo; Tae Whan Kim

doi:10.1109/JEDS.2021.3104843

Effect of the Blocking Oxide Layer with Asymmetric Taper Angles in 3-D NAND Flash Memories

Jun Gyu Lee, Woo Je Jung, Jae Hyeon Park, Keon Ho Yoo, Tae Whan Kim

Research output: Contribution to journal › Article › peer-review

2 Citations (Scopus)

Abstract

The tapered channel effect is a major concern in three-dimensional (3-D) NAND technology because the effect causes differences in the electrical characteristics, including the threshold voltage (VT), between the upper and the lower cells. We simulated the tapered channel effect by using Sentaurus technology, computer-aided design (TCAD) tools, and based on the results, we propose a novel method to lessen the non-uniformity of the threshold voltage shift (ΔV T) between the cells. The difference in Δ V T between the upper and the lower cells due to the tapered channel can be reduced by employing a tapered blocking oxide layer with a proper taper angle. These results will be helpful in designing reliable 3-D NAND flash memories.

Original language	English
Article number	9514533
Pages (from-to)	774-777
Number of pages	4
Journal	IEEE Journal of the Electron Devices Society
Volume	9
DOIs	https://doi.org/10.1109/JEDS.2021.3104843
Publication status	Published - 2021

Keywords

3-D NAND flash memories
tapered channel
threshold voltage shift

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10.1109/JEDS.2021.3104843

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@article{55c8e040e758407b969c40a57af976db,

title = "Effect of the Blocking Oxide Layer with Asymmetric Taper Angles in 3-D NAND Flash Memories",

abstract = "The tapered channel effect is a major concern in three-dimensional (3-D) NAND technology because the effect causes differences in the electrical characteristics, including the threshold voltage (VT), between the upper and the lower cells. We simulated the tapered channel effect by using Sentaurus technology, computer-aided design (TCAD) tools, and based on the results, we propose a novel method to lessen the non-uniformity of the threshold voltage shift (ΔV T) between the cells. The difference in Δ V T between the upper and the lower cells due to the tapered channel can be reduced by employing a tapered blocking oxide layer with a proper taper angle. These results will be helpful in designing reliable 3-D NAND flash memories.",

keywords = "3-D NAND flash memories, tapered channel, threshold voltage shift",

author = "Lee, {Jun Gyu} and Jung, {Woo Je} and Park, {Jae Hyeon} and Yoo, {Keon Ho} and Kim, {Tae Whan}",

note = "Funding Information: This work was supported by IDEC (EDA Tool, MPW). Funding Information: This work was supported by the Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and Technology under Grant 2019R1A2B5B03069968. Publisher Copyright: {\textcopyright} 2013 IEEE.",

year = "2021",

doi = "10.1109/JEDS.2021.3104843",

language = "English",

volume = "9",

pages = "774--777",

journal = "IEEE Journal of the Electron Devices Society",

issn = "2168-6734",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

}

TY - JOUR

T1 - Effect of the Blocking Oxide Layer with Asymmetric Taper Angles in 3-D NAND Flash Memories

AU - Lee, Jun Gyu

AU - Jung, Woo Je

AU - Park, Jae Hyeon

AU - Yoo, Keon Ho

AU - Kim, Tae Whan

N1 - Funding Information: This work was supported by IDEC (EDA Tool, MPW). Funding Information: This work was supported by the Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and Technology under Grant 2019R1A2B5B03069968. Publisher Copyright: © 2013 IEEE.

PY - 2021

Y1 - 2021

N2 - The tapered channel effect is a major concern in three-dimensional (3-D) NAND technology because the effect causes differences in the electrical characteristics, including the threshold voltage (VT), between the upper and the lower cells. We simulated the tapered channel effect by using Sentaurus technology, computer-aided design (TCAD) tools, and based on the results, we propose a novel method to lessen the non-uniformity of the threshold voltage shift (ΔV T) between the cells. The difference in Δ V T between the upper and the lower cells due to the tapered channel can be reduced by employing a tapered blocking oxide layer with a proper taper angle. These results will be helpful in designing reliable 3-D NAND flash memories.

AB - The tapered channel effect is a major concern in three-dimensional (3-D) NAND technology because the effect causes differences in the electrical characteristics, including the threshold voltage (VT), between the upper and the lower cells. We simulated the tapered channel effect by using Sentaurus technology, computer-aided design (TCAD) tools, and based on the results, we propose a novel method to lessen the non-uniformity of the threshold voltage shift (ΔV T) between the cells. The difference in Δ V T between the upper and the lower cells due to the tapered channel can be reduced by employing a tapered blocking oxide layer with a proper taper angle. These results will be helpful in designing reliable 3-D NAND flash memories.

KW - 3-D NAND flash memories

KW - tapered channel

KW - threshold voltage shift

UR - http://www.scopus.com/inward/record.url?scp=85113238943&partnerID=8YFLogxK

U2 - 10.1109/JEDS.2021.3104843

DO - 10.1109/JEDS.2021.3104843

M3 - Article

AN - SCOPUS:85113238943

SN - 2168-6734

VL - 9

SP - 774

EP - 777

JO - IEEE Journal of the Electron Devices Society

JF - IEEE Journal of the Electron Devices Society

M1 - 9514533

ER -

Effect of the Blocking Oxide Layer with Asymmetric Taper Angles in 3-D NAND Flash Memories

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Keywords

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