Electrically modifiable synapse array composed of metal-ferroelectric-semiconductor (MFS) FET's using SrBi2Ta2O9 thin films

Sung Min Yoon; Eisuke Tokumitsu; Hiroshi Ishiwara

doi:10.1109/55.761023

Electrically modifiable synapse array composed of metal-ferroelectric-semiconductor (MFS) FET's using SrBi₂Ta₂O₉ thin films

Sung Min Yoon
, Eisuke Tokumitsu
, Hiroshi Ishiwara

Research output: Contribution to journal › Article › peer-review

41 Citations (Scopus)

Abstract

An array of metal-ferroelectric-semiconductor field effect transistors (MFSFET's) is fabricated on a silicon-on-insulator (SOI) structure using SrBi₂Ta₂O₉ as the gate insulator. It is demonstrated that each FET shows good characteristics as a nonvolatile analog memory due to partial polarization of the SrBi₂Ta₂O₉ film that the array operates as an electrically modifiable synapse circuit for carrying out the weighted sum operation in an artificial neural network.

Original language	English
Pages (from-to)	229-231
Number of pages	3
Journal	IEEE Electron Device Letters
Volume	20
Issue number	5
DOIs	https://doi.org/10.1109/55.761023
Publication status	Published - May 1999

Bibliographical note

Funding Information:
Manuscript received August 31, 1998; revised November 30, 1998. This work was supported by a 1998 Grant-in-Aid for Scientific Research on Priority Area 07248105 and a Grant-in Aid for COE Research on Ultra-Parallel Optoelectronics 07CE2003 from the Ministry of Education, Science, Sports, and Culture in Japan.

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title = "Electrically modifiable synapse array composed of metal-ferroelectric-semiconductor (MFS) FET's using SrBi2Ta2O9 thin films",

abstract = "An array of metal-ferroelectric-semiconductor field effect transistors (MFSFET's) is fabricated on a silicon-on-insulator (SOI) structure using SrBi2Ta2O9 as the gate insulator. It is demonstrated that each FET shows good characteristics as a nonvolatile analog memory due to partial polarization of the SrBi2Ta2O9 film that the array operates as an electrically modifiable synapse circuit for carrying out the weighted sum operation in an artificial neural network.",

author = "Yoon, \{Sung Min\} and Eisuke Tokumitsu and Hiroshi Ishiwara",

note = "Funding Information: Manuscript received August 31, 1998; revised November 30, 1998. This work was supported by a 1998 Grant-in-Aid for Scientific Research on Priority Area 07248105 and a Grant-in Aid for COE Research on Ultra-Parallel Optoelectronics 07CE2003 from the Ministry of Education, Science, Sports, and Culture in Japan.",

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doi = "10.1109/55.761023",

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AU - Yoon, Sung Min

AU - Tokumitsu, Eisuke

AU - Ishiwara, Hiroshi

N1 - Funding Information: Manuscript received August 31, 1998; revised November 30, 1998. This work was supported by a 1998 Grant-in-Aid for Scientific Research on Priority Area 07248105 and a Grant-in Aid for COE Research on Ultra-Parallel Optoelectronics 07CE2003 from the Ministry of Education, Science, Sports, and Culture in Japan.

PY - 1999/5

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N2 - An array of metal-ferroelectric-semiconductor field effect transistors (MFSFET's) is fabricated on a silicon-on-insulator (SOI) structure using SrBi2Ta2O9 as the gate insulator. It is demonstrated that each FET shows good characteristics as a nonvolatile analog memory due to partial polarization of the SrBi2Ta2O9 film that the array operates as an electrically modifiable synapse circuit for carrying out the weighted sum operation in an artificial neural network.

AB - An array of metal-ferroelectric-semiconductor field effect transistors (MFSFET's) is fabricated on a silicon-on-insulator (SOI) structure using SrBi2Ta2O9 as the gate insulator. It is demonstrated that each FET shows good characteristics as a nonvolatile analog memory due to partial polarization of the SrBi2Ta2O9 film that the array operates as an electrically modifiable synapse circuit for carrying out the weighted sum operation in an artificial neural network.

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DO - 10.1109/55.761023

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AN - SCOPUS:0032654956

SN - 0741-3106

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JO - IEEE Electron Device Letters

JF - IEEE Electron Device Letters

IS - 5

ER -

Electrically modifiable synapse array composed of metal-ferroelectric-semiconductor (MFS) FET's using SrBi₂Ta₂O₉ thin films

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