Energy Efficient Electrolytic-Gated Synapse Transistors Using InGaZnO/HfO2Gate Stacks with Vertical Channel Configurations

Dong Hee Kim; Young Ha Kwon; Nak Jin Seong; Kyu Jeong Choi; Jong Heon Yang; Chi Sun Hwang; Sung Min Yoon

doi:10.1109/LED.2024.3424454

Energy Efficient Electrolytic-Gated Synapse Transistors Using InGaZnO/HfO₂Gate Stacks with Vertical Channel Configurations

Dong Hee Kim
, Young Ha Kwon
, Nak Jin Seong
, Kyu Jeong Choi
, Jong Heon Yang
, Chi Sun Hwang
, Sung Min Yoon

Research output: Contribution to journal › Article › peer-review

8 Citations (Scopus)

Abstract

150-nm channel length vertical synapse transistor with oxide channel was demonstrated. The implementation of mesa-Type vertical channels effectively minimized the device footprint, enhancing both the compactness and efficiency. The fabricated vertical synapse transistor exhibited a high on/off ratio of 6.3 × 1010 at a drain bias of 1 V and demonstrated a current drivability of 13.5 μA/μm. The superior on/off ratio ensures minimal leakage current, contributing to enhanced energy efficiency and serving as a strength in multi-levels implementations. In particular, the device has implemented the energy consumption at the fJ-level and 120 multi-levels, highlighting the strong potential of next-generation neuromorphic computing.

Original language	English
Pages (from-to)	1673-1676
Number of pages	4
Journal	IEEE Electron Device Letters
Volume	45
Issue number	9
DOIs	https://doi.org/10.1109/LED.2024.3424454
Publication status	Published - 2024

Bibliographical note

Publisher Copyright:
© 1980-2012 IEEE.

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

Keywords

atomic-layer deposition
Neuromorphic computing
vertical channel synapse transistor

Access to Document

10.1109/LED.2024.3424454

Cite this

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title = "Energy Efficient Electrolytic-Gated Synapse Transistors Using InGaZnO/HfO2Gate Stacks with Vertical Channel Configurations",

abstract = "150-nm channel length vertical synapse transistor with oxide channel was demonstrated. The implementation of mesa-Type vertical channels effectively minimized the device footprint, enhancing both the compactness and efficiency. The fabricated vertical synapse transistor exhibited a high on/off ratio of 6.3 {\texttimes} 1010 at a drain bias of 1 V and demonstrated a current drivability of 13.5 μA/μm. The superior on/off ratio ensures minimal leakage current, contributing to enhanced energy efficiency and serving as a strength in multi-levels implementations. In particular, the device has implemented the energy consumption at the fJ-level and 120 multi-levels, highlighting the strong potential of next-generation neuromorphic computing.",

keywords = "atomic-layer deposition, Neuromorphic computing, vertical channel synapse transistor",

author = "Kim, \{Dong Hee\} and Kwon, \{Young Ha\} and Seong, \{Nak Jin\} and Choi, \{Kyu Jeong\} and Yang, \{Jong Heon\} and Hwang, \{Chi Sun\} and Yoon, \{Sung Min\}",

note = "Publisher Copyright: {\textcopyright} 1980-2012 IEEE.",

year = "2024",

doi = "10.1109/LED.2024.3424454",

language = "English",

volume = "45",

pages = "1673--1676",

journal = "IEEE Electron Device Letters",

issn = "0741-3106",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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T1 - Energy Efficient Electrolytic-Gated Synapse Transistors Using InGaZnO/HfO2Gate Stacks with Vertical Channel Configurations

AU - Kim, Dong Hee

AU - Kwon, Young Ha

AU - Seong, Nak Jin

AU - Choi, Kyu Jeong

AU - Yang, Jong Heon

AU - Hwang, Chi Sun

AU - Yoon, Sung Min

PY - 2024

Y1 - 2024

N2 - 150-nm channel length vertical synapse transistor with oxide channel was demonstrated. The implementation of mesa-Type vertical channels effectively minimized the device footprint, enhancing both the compactness and efficiency. The fabricated vertical synapse transistor exhibited a high on/off ratio of 6.3 × 1010 at a drain bias of 1 V and demonstrated a current drivability of 13.5 μA/μm. The superior on/off ratio ensures minimal leakage current, contributing to enhanced energy efficiency and serving as a strength in multi-levels implementations. In particular, the device has implemented the energy consumption at the fJ-level and 120 multi-levels, highlighting the strong potential of next-generation neuromorphic computing.

AB - 150-nm channel length vertical synapse transistor with oxide channel was demonstrated. The implementation of mesa-Type vertical channels effectively minimized the device footprint, enhancing both the compactness and efficiency. The fabricated vertical synapse transistor exhibited a high on/off ratio of 6.3 × 1010 at a drain bias of 1 V and demonstrated a current drivability of 13.5 μA/μm. The superior on/off ratio ensures minimal leakage current, contributing to enhanced energy efficiency and serving as a strength in multi-levels implementations. In particular, the device has implemented the energy consumption at the fJ-level and 120 multi-levels, highlighting the strong potential of next-generation neuromorphic computing.

KW - atomic-layer deposition

KW - Neuromorphic computing

KW - vertical channel synapse transistor

UR - https://www.scopus.com/pages/publications/85198233577

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DO - 10.1109/LED.2024.3424454

M3 - Article

AN - SCOPUS:85198233577

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VL - 45

SP - 1673

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