Fabrication and characterization of 1T2C-type ferroelectric memory cell

A 1T2C-type ferroelectric memory cell, in which two ferroelectric capacitors with the same area are connected to the gate of an usual MOSFET with a SiO₂/Si interface, was fabricated and characterized. The relations between various device parameters and characteristics of memory cell were investigated by using SPICE simulation. It was found from the simulation results that the memory window significantly changed by the device parameters, which means that the operation voltage of the memory cell can be well controlled by these parameters. The fabricated cell is composed of a stacked gate structure of Pt/SBT/Pt/Ti/SiO₂/Si with the area ratio of the MOS capacitor (S_O) to the ferroelectric capacitor (S_F) of 6 or 10. Nonvolatile memory operation was confirmed, and the obtained memory window coincided with the simulated results qualitatively. Furthermore, the current on/off ratio in the read-out operation was larger than 3-order-of magnitude and the data retention time was longer than 6 × 10⁴ seconds. It was also predicted that low voltage operation was possible if the device parameters were optimized.