Fast Digital Circuit Synthesis Framework Based on Deep Reinforcement Learning Using Scoreboard

In a field of circuit design that uses deep learning such as layout optimization, parameter optimization, and circuit synthesis automation, the proposed framework, fast-GateRL, addresses the digital circuit synthesis automation based on deep reinforcement learning at a CMOS transistor level. The fast-GateRL considers the threshold voltage and avoids shoot-through current paths, whereas the previous GateRL deals with transistors as ideal switches. It also achieves high-speed circuit extraction by mask generation of the prohibited and meaningless connections, intermediate rewards based on a scoreboard, and initial state selection with the trimmed circuit connections. The new connection is generated by the deep neural network to support a deep Q-network. The fast-GateRL is evaluated on 16 two-input digital logic circuits that are verified by SPICE simulation. In addition, the ablation test confirms that scoreboard and initial state selection help the proposed framework reduce the search time for final logic circuits substantially.