High-Performance Dual Gate Amorphous InGaZnO Thin Film Transistor with Top Gate to Drain Offset

Sunaina Priyadarshi, Mohammad Masum Billah, Hyunho Kim, Md Hasnat Rabbi, Sadia Sayed Urmi, Suhui Lee, Jin Jang

Research output: Contribution to journalArticlepeer-review

Abstract

We report the dual gate (DG) amorphous Indium-Gallium-Zinc-Oxide (a-IGZO) thin-film transistor (TFT) with a top-gate (TG) drain offset (LTG(Off)) structure under dual-gate driving. The TFT shows an on/off current ratio of ∼ 107, subthreshold swing of 0.23 V/dec, and field-effect mobility (μFE) of 14.6 cm2/Vs when LTG(Off) is 5 μm, which is 30% reduction compared to the conventional DG TFT with no drain offset (μFE=20.9 cm2/Vs). The Technology computer-aided design simulation indicates the electron concentration of ∼ 1016/cm3 at the offset region near top gate insulator/a-IGZO interface when LTG(Off) is 5 μm. The fabricated TFT exhibits stable performance under positive bias temperature stress with a threshold voltage shift of +0.1 V.

Original languageEnglish
Pages (from-to)56-59
Number of pages4
JournalIEEE Electron Device Letters
Volume43
Issue number1
DOIs
Publication statusPublished - 1 Jan 2022

Keywords

  • a-IGZO
  • drain offset
  • dual gate
  • TCAD
  • technology computer-aided design
  • TFT

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