High-Performance Dual Gate Amorphous InGaZnO Thin Film Transistor with Top Gate to Drain Offset

Sunaina Priyadarshi; Mohammad Masum Billah; Hyunho Kim; Md Hasnat Rabbi; Sadia Sayed Urmi; Suhui Lee; Jin Jang

doi:10.1109/LED.2021.3128940

High-Performance Dual Gate Amorphous InGaZnO Thin Film Transistor with Top Gate to Drain Offset

Sunaina Priyadarshi, Mohammad Masum Billah, Hyunho Kim, Md Hasnat Rabbi, Sadia Sayed Urmi, Suhui Lee, Jin Jang

Research output: Contribution to journal › Article › peer-review

9 Citations (Scopus)

Abstract

We report the dual gate (DG) amorphous Indium-Gallium-Zinc-Oxide (a-IGZO) thin-film transistor (TFT) with a top-gate (TG) drain offset (LTG(Off)) structure under dual-gate driving. The TFT shows an on/off current ratio of ∼ 107, subthreshold swing of 0.23 V/dec, and field-effect mobility (μFE) of 14.6 cm2/Vs when LTG(Off) is 5 μm, which is 30% reduction compared to the conventional DG TFT with no drain offset (μFE=20.9 cm2/Vs). The Technology computer-aided design simulation indicates the electron concentration of ∼ 1016/cm3 at the offset region near top gate insulator/a-IGZO interface when LTG(Off) is 5 μm. The fabricated TFT exhibits stable performance under positive bias temperature stress with a threshold voltage shift of +0.1 V.

Original language	English
Pages (from-to)	56-59
Number of pages	4
Journal	IEEE Electron Device Letters
Volume	43
Issue number	1
DOIs	https://doi.org/10.1109/LED.2021.3128940
Publication status	Published - 1 Jan 2022

Bibliographical note

Publisher Copyright:
© 1980-2012 IEEE.

Keywords

TCAD
TFT
a-IGZO
drain offset
dual gate
technology computer-aided design

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10.1109/LED.2021.3128940

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@article{f97dd5097dd44a85865d99ab4810299b,

title = "High-Performance Dual Gate Amorphous InGaZnO Thin Film Transistor with Top Gate to Drain Offset",

abstract = "We report the dual gate (DG) amorphous Indium-Gallium-Zinc-Oxide (a-IGZO) thin-film transistor (TFT) with a top-gate (TG) drain offset (LTG(Off)) structure under dual-gate driving. The TFT shows an on/off current ratio of ∼ 107, subthreshold swing of 0.23 V/dec, and field-effect mobility (μFE) of 14.6 cm2/Vs when LTG(Off) is 5 μm, which is 30% reduction compared to the conventional DG TFT with no drain offset (μFE=20.9 cm2/Vs). The Technology computer-aided design simulation indicates the electron concentration of ∼ 1016/cm3 at the offset region near top gate insulator/a-IGZO interface when LTG(Off) is 5 μm. The fabricated TFT exhibits stable performance under positive bias temperature stress with a threshold voltage shift of +0.1 V.",

keywords = "TCAD, TFT, a-IGZO, drain offset, dual gate, technology computer-aided design",

author = "Sunaina Priyadarshi and Billah, {Mohammad Masum} and Hyunho Kim and Rabbi, {Md Hasnat} and Urmi, {Sadia Sayed} and Suhui Lee and Jin Jang",

note = "Publisher Copyright: {\textcopyright} 1980-2012 IEEE.",

year = "2022",

month = jan,

day = "1",

doi = "10.1109/LED.2021.3128940",

language = "English",

volume = "43",

pages = "56--59",

journal = "IEEE Electron Device Letters",

issn = "0741-3106",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "1",

}

TY - JOUR

T1 - High-Performance Dual Gate Amorphous InGaZnO Thin Film Transistor with Top Gate to Drain Offset

AU - Priyadarshi, Sunaina

AU - Billah, Mohammad Masum

AU - Kim, Hyunho

AU - Rabbi, Md Hasnat

AU - Urmi, Sadia Sayed

AU - Lee, Suhui

AU - Jang, Jin

PY - 2022/1/1

Y1 - 2022/1/1

N2 - We report the dual gate (DG) amorphous Indium-Gallium-Zinc-Oxide (a-IGZO) thin-film transistor (TFT) with a top-gate (TG) drain offset (LTG(Off)) structure under dual-gate driving. The TFT shows an on/off current ratio of ∼ 107, subthreshold swing of 0.23 V/dec, and field-effect mobility (μFE) of 14.6 cm2/Vs when LTG(Off) is 5 μm, which is 30% reduction compared to the conventional DG TFT with no drain offset (μFE=20.9 cm2/Vs). The Technology computer-aided design simulation indicates the electron concentration of ∼ 1016/cm3 at the offset region near top gate insulator/a-IGZO interface when LTG(Off) is 5 μm. The fabricated TFT exhibits stable performance under positive bias temperature stress with a threshold voltage shift of +0.1 V.

AB - We report the dual gate (DG) amorphous Indium-Gallium-Zinc-Oxide (a-IGZO) thin-film transistor (TFT) with a top-gate (TG) drain offset (LTG(Off)) structure under dual-gate driving. The TFT shows an on/off current ratio of ∼ 107, subthreshold swing of 0.23 V/dec, and field-effect mobility (μFE) of 14.6 cm2/Vs when LTG(Off) is 5 μm, which is 30% reduction compared to the conventional DG TFT with no drain offset (μFE=20.9 cm2/Vs). The Technology computer-aided design simulation indicates the electron concentration of ∼ 1016/cm3 at the offset region near top gate insulator/a-IGZO interface when LTG(Off) is 5 μm. The fabricated TFT exhibits stable performance under positive bias temperature stress with a threshold voltage shift of +0.1 V.

KW - TCAD

KW - TFT

KW - a-IGZO

KW - drain offset

KW - dual gate

KW - technology computer-aided design

UR - http://www.scopus.com/inward/record.url?scp=85120037356&partnerID=8YFLogxK

U2 - 10.1109/LED.2021.3128940

DO - 10.1109/LED.2021.3128940

M3 - Article

AN - SCOPUS:85120037356

SN - 0741-3106

VL - 43

SP - 56

EP - 59

JO - IEEE Electron Device Letters

JF - IEEE Electron Device Letters

IS - 1

ER -

High-Performance Dual Gate Amorphous InGaZnO Thin Film Transistor with Top Gate to Drain Offset

Abstract

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Keywords

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