Hysteresis behavior in pentacene organic thin-film transistors

Myeong Seob So, Min Chul Suh, Jae Bon Koo, Byoung Deog Choi, Dae Chul Choi, Hun Jung Lee, Yeon Gon Mo, Ho Kyoon Chung

Research output: Contribution to journalConference articlepeer-review

1 Citation (Scopus)

Abstract

In this paper, we have identified the mechanism of C-V hysteresis behavior often observed in pentacene organic thin-film transistors (OTFTs). The capacitance-voltage (C-V) characteristics were measured for pentacene OTFTs fabricated on glass substrates with MoW as gate/source/drain electrode and TEOS SiO2 as gate insulator. The measurements were made at room temperature and elevated temperatures. From the room temperature measurements, we found that the hysteresis behavior was caused by hole injection into the gate insulator from the pentacene semiconductor for large negative gate voltages, resulting in the negative flat-band voltage shift. However electron injection was observed only at elevated temperatures.

Original languageEnglish
Pages (from-to)1364-1369
Number of pages6
JournalProceedings of International Meeting on Information Display
Volume2
Publication statusPublished - 2006
Event5th International Meeting on Information Display - Seoul, Korea, Republic of
Duration: 19 Jul 200523 Jul 2005

Fingerprint

Dive into the research topics of 'Hysteresis behavior in pentacene organic thin-film transistors'. Together they form a unique fingerprint.

Cite this