Multi-Level Memory Comprising Lowerature Poly-Silicon and Oxide TFTs

In this letter, a new multi-level memory cell using lowerature polycrystalline silicon and oxide (LTPO) thin-film transistor (TFT) backplane is proposed. The multi-bit data storage can be achieved with a simple structure of two transistors and a capacitor, which controls the threshold voltage of a memory cell transistor exactly. In a memory cell, the lowerature polycrystalline silicon (LTPS) TFT provides excellent stability against bias stress or current stress. In addition, the oxide semiconductor TFT enables the long-term data storage by virtue of its extremely low off-state leakage current. The proposed memory is fabricated with the LTPO TFT process which includes p-type LTPS and n-type oxide TFTs. Furthermore, the implementation of the multi-level property is successfully verified by measured results.