Performance improvement of polycrystalline thin-film transistor by adopting a very thin amorphous silicon buffer

Kyung Wook Kim; Kyu Sik Cho; Jin Jang

doi:10.1016/s0022-3093(99)00935-7

Performance improvement of polycrystalline thin-film transistor by adopting a very thin amorphous silicon buffer

Kyung Wook Kim
, Kyu Sik Cho
, Jin Jang

Research output: Contribution to journal › Conference article › peer-review

10 Citations (Scopus)

Abstract

A novel polycrystalline thin-film transistor (TFT) with a very thin (<10 nm) a-Si:H buffer has been studied. The offstate leakage current of the coplanar polycrystalline silicon (poly-Si) TFT was reduced using quadruple layers of a-Si:H, SiN_x, thinner a-Si:H and poly-Si and by simultaneous silicide formation of the source, drain and gate contacts. While offset-gate and lightly doped drain (LDD) poly-Si TFT structures require additional mask steps to form the field-reduced regions, the proposed poly-Si TFT needs only 2 photo-mask steps. The on-off current ratio increases from 10⁶ to 10⁸ by adopting a thinner a-Si:H buffer on the poly-Si.

Original language	English
Pages (from-to)	1265-1269
Number of pages	5
Journal	Journal of Non-Crystalline Solids
Volume	266-269 B
DOIs	https://doi.org/10.1016/s0022-3093(99)00935-7
Publication status	Published - 1 May 2000
Event	18th International Conference on Amorphous and Microcrystalline Semiconductors - Sicence and Technology (ICAMS 18) - Snowbird, UT, United States Duration: 23 Aug 1999 → 27 Aug 1999

Bibliographical note

Funding Information:
This work was supported by the Electronics and Telecommunications Research Institute and the Ministry of Information and Communications, Korea.

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10.1016/s0022-3093(99)00935-7

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title = "Performance improvement of polycrystalline thin-film transistor by adopting a very thin amorphous silicon buffer",

abstract = "A novel polycrystalline thin-film transistor (TFT) with a very thin (<10 nm) a-Si:H buffer has been studied. The offstate leakage current of the coplanar polycrystalline silicon (poly-Si) TFT was reduced using quadruple layers of a-Si:H, SiNx, thinner a-Si:H and poly-Si and by simultaneous silicide formation of the source, drain and gate contacts. While offset-gate and lightly doped drain (LDD) poly-Si TFT structures require additional mask steps to form the field-reduced regions, the proposed poly-Si TFT needs only 2 photo-mask steps. The on-off current ratio increases from 106 to 108 by adopting a thinner a-Si:H buffer on the poly-Si.",

author = "Kim, \{Kyung Wook\} and Cho, \{Kyu Sik\} and Jin Jang",

note = "Funding Information: This work was supported by the Electronics and Telecommunications Research Institute and the Ministry of Information and Communications, Korea. ; 18th International Conference on Amorphous and Microcrystalline Semiconductors - Sicence and Technology (ICAMS 18) ; Conference date: 23-08-1999 Through 27-08-1999",

year = "2000",

month = may,

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doi = "10.1016/s0022-3093(99)00935-7",

language = "English",

volume = "266-269 B",

pages = "1265--1269",

journal = "Journal of Non-Crystalline Solids",

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TY - JOUR

T1 - Performance improvement of polycrystalline thin-film transistor by adopting a very thin amorphous silicon buffer

AU - Kim, Kyung Wook

AU - Cho, Kyu Sik

AU - Jang, Jin

N1 - Funding Information: This work was supported by the Electronics and Telecommunications Research Institute and the Ministry of Information and Communications, Korea.

PY - 2000/5/1

Y1 - 2000/5/1

N2 - A novel polycrystalline thin-film transistor (TFT) with a very thin (<10 nm) a-Si:H buffer has been studied. The offstate leakage current of the coplanar polycrystalline silicon (poly-Si) TFT was reduced using quadruple layers of a-Si:H, SiNx, thinner a-Si:H and poly-Si and by simultaneous silicide formation of the source, drain and gate contacts. While offset-gate and lightly doped drain (LDD) poly-Si TFT structures require additional mask steps to form the field-reduced regions, the proposed poly-Si TFT needs only 2 photo-mask steps. The on-off current ratio increases from 106 to 108 by adopting a thinner a-Si:H buffer on the poly-Si.

AB - A novel polycrystalline thin-film transistor (TFT) with a very thin (<10 nm) a-Si:H buffer has been studied. The offstate leakage current of the coplanar polycrystalline silicon (poly-Si) TFT was reduced using quadruple layers of a-Si:H, SiNx, thinner a-Si:H and poly-Si and by simultaneous silicide formation of the source, drain and gate contacts. While offset-gate and lightly doped drain (LDD) poly-Si TFT structures require additional mask steps to form the field-reduced regions, the proposed poly-Si TFT needs only 2 photo-mask steps. The on-off current ratio increases from 106 to 108 by adopting a thinner a-Si:H buffer on the poly-Si.

UR - https://www.scopus.com/pages/publications/0347112305

U2 - 10.1016/s0022-3093(99)00935-7

DO - 10.1016/s0022-3093(99)00935-7

M3 - Conference article

AN - SCOPUS:0347112305

SN - 0022-3093

VL - 266-269 B

SP - 1265

EP - 1269

JO - Journal of Non-Crystalline Solids

JF - Journal of Non-Crystalline Solids

T2 - 18th International Conference on Amorphous and Microcrystalline Semiconductors - Sicence and Technology (ICAMS 18)

Y2 - 23 August 1999 through 27 August 1999

ER -

Performance improvement of polycrystalline thin-film transistor by adopting a very thin amorphous silicon buffer

Abstract

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