Pin Accessibility and Routing Congestion Aware DRC Hotspot Prediction for Designs in Advanced Technology Nodes With Consolidated Practical Applicability and Sustainability

Advanced technology nodes face challenges related to design rule violations (DRVs), primarily due to (1) pin inaccessibility and routing on congested region. While various machine learning (ML) techniques have been introduced to address these issues during placement, aggregating data on pin accessibility and routing congestion for ML model training has proven very challenging. This study presents an innovative ML-based approach to design rule check (DRC) hotspot prediction that effectively captures the combined impact of pin accessibility and routing congestion. Specifically, we introduce the concept of pin proximity graph, which accurately represents spatial information regarding cell I/O pins and pin-to-pin disturbance relationships. We then propose a novel ML model called PGNN, which seamlessly integrates graph neural network (GNN) and U-net. In this approach, GNN handles the incorporation of pin accessibility information derived from the pin proximity graph while U-net extracts routing congestion information from grid-based features. Additionally, we solidify the capability of our prediction model toward ensuring the practical applicability and sustainability of our model by integrating two learning methodologies into our model training framework. Those are 1) transfer learning whose objective is to retain the same level of prediction accuracy in spite of not having enough data on the new process node and 2) incremental learning whose objective is to reduce the train time while maintaining the model accuracy in similar quality when new circuits are added.