Process design for improvement in device performance of top-gate TFTs using In-Sn-Zn-O channels prepared by thermal atomic-layer deposition

Top-gate (TG) thin-film transistors (TFTs) employing In-Sn-Zn-O (ITZO) as a channel by thermal atomic-layer deposition were fabricated and their device characteristics and long-term operational stability were compared with variations in process conditions for the formation of active and gate insulator (GI) layers. The optimal device characteristics were obtained as a field-effect mobility of 60.0 cm²/Vs, a threshold voltage of +0.5 V, and a subthreshold swing of 0.138 V/dec, which were achieved by depositing ITZO at 250 °C and adjusting the thickness and deposition temperature of GI to 40 nm and 300 °C, respectively. The long-term operational stability under positive-bias-temperature-stress (PBTS) was evaluated at an electric field of 2 MV/cm and a thermal stress of 80 °C for 10,000 s. All devices demonstrated remarkable PB(T)S reliability, exhibiting a threshold voltage shift of less than 1 V. Anomalous negative shifts of the threshold voltage (ΔV_TH) were identified during the PB(T)S, and this was attributed to the localization of Sn due to the difference in channel composition and hydrogen incorporation during the GI deposition. A Spectroscopy ellipsometry analysis was conducted to elucidate the origin of the negative ΔV_TH by investigating the band-edge structure. As the process temperature and GI thickness increased, the D1 and D2 states increased and remained consistent, which contribute to the conduction carriers and to charge trapping, respectively, thereby elucidating the origin of the enhanced device characteristics. The findings reveal the impact of the channel deposition process as well as the processes followed by the formation of the active layer, which were accompanied by thermal annealing, for the TG ITZO TFTs, leading to improved device characteristics and good long-term operational stability.