Properties of bottom and top channel interfaces in double-gate back-channel-etched amorphous indium-gallium-zinc oxide thin-film transistors

In this paper, the bottom and top channel interface properties are investigated in the back channel etch-type double-gate amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors. The authors apply the subthreshold technique by depleting one channel, while sweeping the gate voltage of the opposite channel to separately characterize the bottom and top channel interfaces. The extracted surface energy distribution of the bottom and top channel interface trap densities is well fitted with an exponential distribution, and the top channel interface trap density is found to be around 2.5 times greater than that of the bottom channel interface at the conduction band edge. This is mainly attributed to the poor quality of the top gate SiO_x insulator owing to the low plasma-enhanced chemical vapor deposition temperature or to the defect generation at the back surface of the a-IGZO caused by the plasma damage during the top gate SiO_x insulator deposition. The electrons are shown to be more easily trapped at the top channel interface than at the bottom channel interface under high gate bias stresses in the fabricated back channel etch-type double-gate a-IGZO thin-film transistors.