Removal of negative-bias-illumination-stress instability in amorphous-InGaZnO thin-film transistors by top-gate offset structure

Suhui Lee; Mallory Mativenga; Jin Jang

doi:10.1109/LED.2014.2333014

Removal of negative-bias-illumination-stress instability in amorphous-InGaZnO thin-film transistors by top-gate offset structure

Suhui Lee
, Mallory Mativenga
, Jin Jang

Research output: Contribution to journal › Article › peer-review

68 Citations (Scopus)

Abstract

A highly stable, dual-gate (DG) amorphous, indium-gallium-zinc oxide (a-IGZO) thin-film transistor (TFT) with an offset top-gate (TG) is reported. Given that both gates are opaque and electrically tied together, the TG functions as a light-shield and drain-current (I_DS) enhancer as synchronized gate-voltage (V_GS) sweep induces bulk-accumulation (BA) at positive voltages. It is demonstrated here that regardless of the offsets between the TG and source/drain electrode, this BA a-IGZO TFT is immune to negative bias and light-illumination stress (NBIS) when the TG covers at least 50% of the channel region. Therefore, high performance BA a-IGZO TFTs that are also immune to NBIS can be designed without introducing additional parasitic capacitance that occurs when the TG overlaps the source and/or drain electrode(s).

Original language	English
Article number	6853385
Pages (from-to)	930-932
Number of pages	3
Journal	IEEE Electron Device Letters
Volume	35
Issue number	9
DOIs	https://doi.org/10.1109/LED.2014.2333014
Publication status	Published - Sept 2014

Keywords

a-IGZO
bulk accumulation
dual gate
negative bias illumination stress (NBIS)
thin film transistor (TFT).

Access to Document

10.1109/LED.2014.2333014

Cite this

@article{270de08ce7674377998d61bc7c6bb0b9,

title = "Removal of negative-bias-illumination-stress instability in amorphous-InGaZnO thin-film transistors by top-gate offset structure",

abstract = "A highly stable, dual-gate (DG) amorphous, indium-gallium-zinc oxide (a-IGZO) thin-film transistor (TFT) with an offset top-gate (TG) is reported. Given that both gates are opaque and electrically tied together, the TG functions as a light-shield and drain-current (IDS) enhancer as synchronized gate-voltage (VGS) sweep induces bulk-accumulation (BA) at positive voltages. It is demonstrated here that regardless of the offsets between the TG and source/drain electrode, this BA a-IGZO TFT is immune to negative bias and light-illumination stress (NBIS) when the TG covers at least 50\% of the channel region. Therefore, high performance BA a-IGZO TFTs that are also immune to NBIS can be designed without introducing additional parasitic capacitance that occurs when the TG overlaps the source and/or drain electrode(s).",

keywords = "a-IGZO, bulk accumulation, dual gate, negative bias illumination stress (NBIS), thin film transistor (TFT).",

author = "Suhui Lee and Mallory Mativenga and Jin Jang",

year = "2014",

month = sep,

doi = "10.1109/LED.2014.2333014",

language = "English",

volume = "35",

pages = "930--932",

journal = "IEEE Electron Device Letters",

issn = "0741-3106",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "9",

}

TY - JOUR

T1 - Removal of negative-bias-illumination-stress instability in amorphous-InGaZnO thin-film transistors by top-gate offset structure

AU - Lee, Suhui

AU - Mativenga, Mallory

AU - Jang, Jin

PY - 2014/9

Y1 - 2014/9

N2 - A highly stable, dual-gate (DG) amorphous, indium-gallium-zinc oxide (a-IGZO) thin-film transistor (TFT) with an offset top-gate (TG) is reported. Given that both gates are opaque and electrically tied together, the TG functions as a light-shield and drain-current (IDS) enhancer as synchronized gate-voltage (VGS) sweep induces bulk-accumulation (BA) at positive voltages. It is demonstrated here that regardless of the offsets between the TG and source/drain electrode, this BA a-IGZO TFT is immune to negative bias and light-illumination stress (NBIS) when the TG covers at least 50% of the channel region. Therefore, high performance BA a-IGZO TFTs that are also immune to NBIS can be designed without introducing additional parasitic capacitance that occurs when the TG overlaps the source and/or drain electrode(s).

AB - A highly stable, dual-gate (DG) amorphous, indium-gallium-zinc oxide (a-IGZO) thin-film transistor (TFT) with an offset top-gate (TG) is reported. Given that both gates are opaque and electrically tied together, the TG functions as a light-shield and drain-current (IDS) enhancer as synchronized gate-voltage (VGS) sweep induces bulk-accumulation (BA) at positive voltages. It is demonstrated here that regardless of the offsets between the TG and source/drain electrode, this BA a-IGZO TFT is immune to negative bias and light-illumination stress (NBIS) when the TG covers at least 50% of the channel region. Therefore, high performance BA a-IGZO TFTs that are also immune to NBIS can be designed without introducing additional parasitic capacitance that occurs when the TG overlaps the source and/or drain electrode(s).

KW - a-IGZO

KW - bulk accumulation

KW - dual gate

KW - negative bias illumination stress (NBIS)

KW - thin film transistor (TFT).

UR - https://www.scopus.com/pages/publications/84906951665

U2 - 10.1109/LED.2014.2333014

DO - 10.1109/LED.2014.2333014

M3 - Article

AN - SCOPUS:84906951665

SN - 0741-3106

VL - 35

SP - 930

EP - 932

JO - IEEE Electron Device Letters

JF - IEEE Electron Device Letters

IS - 9

M1 - 6853385

ER -

Removal of negative-bias-illumination-stress instability in amorphous-InGaZnO thin-film transistors by top-gate offset structure

Abstract

Keywords

Access to Document

Other files and links

Fingerprint

Cite this