STT-MRAM architecture with parallel accumulator for in-memory binary neural networks

Thi Nhan Pham; Quang Kien Trinh; Ik Joon Chang; Massimo Alioto

doi:10.1109/ISCAS51556.2021.9401695

STT-MRAM architecture with parallel accumulator for in-memory binary neural networks

Thi Nhan Pham
, Quang Kien Trinh
, Ik Joon Chang
, Massimo Alioto

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

13 Citations (Scopus)

Abstract

In this paper, a row-wise XNOR accumulator architecture for STT-MRAM arrays is proposed for parallel and efficient multiply-and-accumulate (MAC) operation. The proposed accumulator supports in-memory computing and binary neural network (BNN) applications. In the proposed architecture, inputs are fed from the complementary bitlines, whereas readout is performed through a time-based sense amplifier (TBS). The proposed architecture that does not require any ADC can exhibit an average error rate of 0.085 for XNOR vector size (i.e., accumulate capacity) of 128 bits, which translates into 98.45% classification accuracy of a multi-layer perceptron (MLP) on the MNIST dataset.

Original language	English
Title of host publication	2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781728192017
DOIs	https://doi.org/10.1109/ISCAS51556.2021.9401695
Publication status	Published - 2021
Event	53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Daegu, Korea, Republic of Duration: 22 May 2021 → 28 May 2021

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	2021-May
ISSN (Print)	0271-4310

Conference

Conference	53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021
Country/Territory	Korea, Republic of
City	Daegu
Period	22/05/21 → 28/05/21

Bibliographical note

Publisher Copyright:
© 2021 IEEE

Keywords

In-memory computing
Multiply-and-accumulate
STT-MRAM
XNOR accumulation

Access to Document

10.1109/ISCAS51556.2021.9401695

Cite this

Pham, T. N., Trinh, Q. K., Chang, I. J., & Alioto, M. (2021). STT-MRAM architecture with parallel accumulator for in-memory binary neural networks. In 2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings Article 9401695 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2021-May). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS51556.2021.9401695

@inproceedings{e584f1aa358349529f5772b7be273971,

title = "STT-MRAM architecture with parallel accumulator for in-memory binary neural networks",

abstract = "In this paper, a row-wise XNOR accumulator architecture for STT-MRAM arrays is proposed for parallel and efficient multiply-and-accumulate (MAC) operation. The proposed accumulator supports in-memory computing and binary neural network (BNN) applications. In the proposed architecture, inputs are fed from the complementary bitlines, whereas readout is performed through a time-based sense amplifier (TBS). The proposed architecture that does not require any ADC can exhibit an average error rate of 0.085 for XNOR vector size (i.e., accumulate capacity) of 128 bits, which translates into 98.45\% classification accuracy of a multi-layer perceptron (MLP) on the MNIST dataset.",

keywords = "In-memory computing, Multiply-and-accumulate, STT-MRAM, XNOR accumulation",

author = "Pham, \{Thi Nhan\} and Trinh, \{Quang Kien\} and Chang, \{Ik Joon\} and Massimo Alioto",

note = "Publisher Copyright: {\textcopyright} 2021 IEEE; 53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021 ; Conference date: 22-05-2021 Through 28-05-2021",

year = "2021",

doi = "10.1109/ISCAS51556.2021.9401695",

language = "English",

series = "Proceedings - IEEE International Symposium on Circuits and Systems",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings",

address = "United States",

}

Pham, TN, Trinh, QK, Chang, IJ & Alioto, M 2021, STT-MRAM architecture with parallel accumulator for in-memory binary neural networks. in 2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings., 9401695, Proceedings - IEEE International Symposium on Circuits and Systems, vol. 2021-May, Institute of Electrical and Electronics Engineers Inc., 53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021, Daegu, Korea, Republic of, 22/05/21. https://doi.org/10.1109/ISCAS51556.2021.9401695

STT-MRAM architecture with parallel accumulator for in-memory binary neural networks. / Pham, Thi Nhan; Trinh, Quang Kien; Chang, Ik Joon et al.
2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2021. 9401695 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2021-May).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - STT-MRAM architecture with parallel accumulator for in-memory binary neural networks

AU - Pham, Thi Nhan

AU - Trinh, Quang Kien

AU - Chang, Ik Joon

AU - Alioto, Massimo

PY - 2021

Y1 - 2021

N2 - In this paper, a row-wise XNOR accumulator architecture for STT-MRAM arrays is proposed for parallel and efficient multiply-and-accumulate (MAC) operation. The proposed accumulator supports in-memory computing and binary neural network (BNN) applications. In the proposed architecture, inputs are fed from the complementary bitlines, whereas readout is performed through a time-based sense amplifier (TBS). The proposed architecture that does not require any ADC can exhibit an average error rate of 0.085 for XNOR vector size (i.e., accumulate capacity) of 128 bits, which translates into 98.45% classification accuracy of a multi-layer perceptron (MLP) on the MNIST dataset.

AB - In this paper, a row-wise XNOR accumulator architecture for STT-MRAM arrays is proposed for parallel and efficient multiply-and-accumulate (MAC) operation. The proposed accumulator supports in-memory computing and binary neural network (BNN) applications. In the proposed architecture, inputs are fed from the complementary bitlines, whereas readout is performed through a time-based sense amplifier (TBS). The proposed architecture that does not require any ADC can exhibit an average error rate of 0.085 for XNOR vector size (i.e., accumulate capacity) of 128 bits, which translates into 98.45% classification accuracy of a multi-layer perceptron (MLP) on the MNIST dataset.

KW - In-memory computing

KW - Multiply-and-accumulate

KW - STT-MRAM

KW - XNOR accumulation

UR - https://www.scopus.com/pages/publications/85109023962

U2 - 10.1109/ISCAS51556.2021.9401695

DO - 10.1109/ISCAS51556.2021.9401695

M3 - Conference contribution

AN - SCOPUS:85109023962

T3 - Proceedings - IEEE International Symposium on Circuits and Systems

BT - 2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021

Y2 - 22 May 2021 through 28 May 2021

ER -

Pham TN, Trinh QK, Chang IJ, Alioto M. STT-MRAM architecture with parallel accumulator for in-memory binary neural networks. In 2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2021. 9401695. (Proceedings - IEEE International Symposium on Circuits and Systems). doi: 10.1109/ISCAS51556.2021.9401695

STT-MRAM architecture with parallel accumulator for in-memory binary neural networks

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