The 1/f noise performance for TFTs fabricated in three TFT technologies: Monocrystalline silicon on glass, low temperature polysilicon on glass, and silicon on insulator

The 1/f noise characteristics were measured for CMOS devices fabricated in three different process technologies: conventional SOI, monocrystalline silicon on glass (Corning® Silicon-on-Glass, or SiOG) and low temperature polysilicon (LTPS). Noise slope and bias current parameters, from the SPICE2 low frequency noise model, were extracted from the 1/f measurements. The SPICE2 noise coefficient parameter, K_f, was extracted for each device. SOI PMOS (which exhibit the least amount of 1/f noise) establish a baseline noise level to compare TFT technologies against. SiOG and LTPS PMOS devices exhibit noise coefficients that were 1.89 and 2.93 times larger than the SOI PMOS device, respectively. The degraded 1/f performance of SiOG and LTPS devices when compared to SOI can be linked to the silicon-silicon dioxide interface trap density. All devices exhibited similar 1/f noise slopes, between 0.8 and 0.98, where processing variations were found to correspond to low slope values.