Transistor Sizing Scheme for DICE-Based Radiation-Resilient Latches

Jung Jin Park; Young Min Kang; Geon Hak Kim; Ik Joon Chang; Jinsang Kim

doi:10.1109/ICEIC57457.2023.10049983

Transistor Sizing Scheme for DICE-Based Radiation-Resilient Latches

Jung Jin Park, Young Min Kang, Geon Hak Kim, Ik Joon Chang, Jinsang Kim

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Citation (Scopus)

Abstract

Recently, radiation-aware latch designs have been increasingly important due to the aggressive VLSI scaling. From radiation, latched data can be flipped due to single event upset (SEU) at a single node or multiple nodes in a circuit. Therefore, we need to develop SEU-resilient latches. DICE-based latches has remarkable features during SEU recovery. To our knowledge, there is no systematic analysis of transistor sizes for the DICE-based latch designs. In this paper, we propose transistor sizing scheme for radiation-resilient latches to single node upset and multiple node upsets.

Original language	English
Title of host publication	2023 International Conference on Electronics, Information, and Communication, ICEIC 2023
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9798350320213
DOIs	https://doi.org/10.1109/ICEIC57457.2023.10049983
Publication status	Published - 2023
Event	2023 International Conference on Electronics, Information, and Communication, ICEIC 2023 - Singapore, Singapore Duration: 5 Feb 2023 → 8 Feb 2023

Publication series

Name	2023 International Conference on Electronics, Information, and Communication, ICEIC 2023

Conference

Conference	2023 International Conference on Electronics, Information, and Communication, ICEIC 2023
Country/Territory	Singapore
City	Singapore
Period	5/02/23 → 8/02/23

Bibliographical note

Publisher Copyright:
© 2023 IEEE.

Keywords

DICE
double-node upset (DNU)
radiation-hardened latch
single-node upset (SNU)
soft error

Access to Document

10.1109/ICEIC57457.2023.10049983

Cite this

Park, J. J., Kang, Y. M., Kim, G. H., Chang, I. J., & Kim, J. (2023). Transistor Sizing Scheme for DICE-Based Radiation-Resilient Latches. In 2023 International Conference on Electronics, Information, and Communication, ICEIC 2023 (2023 International Conference on Electronics, Information, and Communication, ICEIC 2023). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICEIC57457.2023.10049983

Park, Jung Jin ; Kang, Young Min ; Kim, Geon Hak et al. / Transistor Sizing Scheme for DICE-Based Radiation-Resilient Latches. 2023 International Conference on Electronics, Information, and Communication, ICEIC 2023. Institute of Electrical and Electronics Engineers Inc., 2023. (2023 International Conference on Electronics, Information, and Communication, ICEIC 2023).

@inproceedings{3439f28911fb47ca8d1b319a71742b30,

title = "Transistor Sizing Scheme for DICE-Based Radiation-Resilient Latches",

abstract = "Recently, radiation-aware latch designs have been increasingly important due to the aggressive VLSI scaling. From radiation, latched data can be flipped due to single event upset (SEU) at a single node or multiple nodes in a circuit. Therefore, we need to develop SEU-resilient latches. DICE-based latches has remarkable features during SEU recovery. To our knowledge, there is no systematic analysis of transistor sizes for the DICE-based latch designs. In this paper, we propose transistor sizing scheme for radiation-resilient latches to single node upset and multiple node upsets.",

keywords = "DICE, double-node upset (DNU), radiation-hardened latch, single-node upset (SNU), soft error",

author = "Park, {Jung Jin} and Kang, {Young Min} and Kim, {Geon Hak} and Chang, {Ik Joon} and Jinsang Kim",

note = "Publisher Copyright: {\textcopyright} 2023 IEEE.; 2023 International Conference on Electronics, Information, and Communication, ICEIC 2023 ; Conference date: 05-02-2023 Through 08-02-2023",

year = "2023",

doi = "10.1109/ICEIC57457.2023.10049983",

language = "English",

series = "2023 International Conference on Electronics, Information, and Communication, ICEIC 2023",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2023 International Conference on Electronics, Information, and Communication, ICEIC 2023",

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}

Park, JJ, Kang, YM, Kim, GH, Chang, IJ & Kim, J 2023, Transistor Sizing Scheme for DICE-Based Radiation-Resilient Latches. in 2023 International Conference on Electronics, Information, and Communication, ICEIC 2023. 2023 International Conference on Electronics, Information, and Communication, ICEIC 2023, Institute of Electrical and Electronics Engineers Inc., 2023 International Conference on Electronics, Information, and Communication, ICEIC 2023, Singapore, Singapore, 5/02/23. https://doi.org/10.1109/ICEIC57457.2023.10049983

Transistor Sizing Scheme for DICE-Based Radiation-Resilient Latches. / Park, Jung Jin; Kang, Young Min; Kim, Geon Hak et al.
2023 International Conference on Electronics, Information, and Communication, ICEIC 2023. Institute of Electrical and Electronics Engineers Inc., 2023. (2023 International Conference on Electronics, Information, and Communication, ICEIC 2023).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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T1 - Transistor Sizing Scheme for DICE-Based Radiation-Resilient Latches

AU - Park, Jung Jin

AU - Kang, Young Min

AU - Kim, Geon Hak

AU - Chang, Ik Joon

AU - Kim, Jinsang

PY - 2023

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N2 - Recently, radiation-aware latch designs have been increasingly important due to the aggressive VLSI scaling. From radiation, latched data can be flipped due to single event upset (SEU) at a single node or multiple nodes in a circuit. Therefore, we need to develop SEU-resilient latches. DICE-based latches has remarkable features during SEU recovery. To our knowledge, there is no systematic analysis of transistor sizes for the DICE-based latch designs. In this paper, we propose transistor sizing scheme for radiation-resilient latches to single node upset and multiple node upsets.

AB - Recently, radiation-aware latch designs have been increasingly important due to the aggressive VLSI scaling. From radiation, latched data can be flipped due to single event upset (SEU) at a single node or multiple nodes in a circuit. Therefore, we need to develop SEU-resilient latches. DICE-based latches has remarkable features during SEU recovery. To our knowledge, there is no systematic analysis of transistor sizes for the DICE-based latch designs. In this paper, we propose transistor sizing scheme for radiation-resilient latches to single node upset and multiple node upsets.

KW - DICE

KW - double-node upset (DNU)

KW - radiation-hardened latch

KW - single-node upset (SNU)

KW - soft error

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M3 - Conference contribution

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BT - 2023 International Conference on Electronics, Information, and Communication, ICEIC 2023

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Park JJ, Kang YM, Kim GH, Chang IJ , Kim J. Transistor Sizing Scheme for DICE-Based Radiation-Resilient Latches. In 2023 International Conference on Electronics, Information, and Communication, ICEIC 2023. Institute of Electrical and Electronics Engineers Inc. 2023. (2023 International Conference on Electronics, Information, and Communication, ICEIC 2023). doi: 10.1109/ICEIC57457.2023.10049983

Transistor Sizing Scheme for DICE-Based Radiation-Resilient Latches

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Keywords

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