Vertically integrated, double-stack oxide-TFT layers for high-resolution AMOLED backplane

Suhui Lee; Yuanfeng Chen; Jeonggi Kim; Jin Jang

doi:10.1002/sdtp.14019

Vertically integrated, double-stack oxide-TFT layers for high-resolution AMOLED backplane

Suhui Lee, Yuanfeng Chen, Jeonggi Kim, Jin Jang

Research output: Contribution to journal › Conference article › peer-review

Abstract

We developed a novel vertically integrated, double stack oxide thin-film transistor (TFT) backplane for high resolution organic light-emitting diode (OLED) displays. The 1st TFT layer is bulk-accumulation mode and 2nd TFT layer is a single gate with back-channel etched structure. The extracted mobilities and threshold voltages are higher than 10 cm²/Vs and 0~1V, respectively. Both TFTs are found to be extremely stable under the bias and temperature stress. The gate driver with width of 530 µm and a pitch of 18.6 µm was developed exhibiting well shifted signal up to the last stage of 900-stages without output degradation, which could be used for 1360ppi, TFT backplane.

Original language	English
Pages (from-to)	913-916
Number of pages	4
Journal	Digest of Technical Papers - SID International Symposium
Volume	51
Issue number	1
DOIs	https://doi.org/10.1002/sdtp.14019
Publication status	Published - 2020
Event	57th SID International Symposium, Seminar and Exhibition, Display Week, 2020 - Virtual, Online Duration: 3 Aug 2020 → 7 Aug 2020

Bibliographical note

Publisher Copyright:
© 2020 SID.

Keywords

Double stack structures
High definition
High resolution
Oxide
Thin-film transistor (TFT)

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10.1002/sdtp.14019

Cite this

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title = "Vertically integrated, double-stack oxide-TFT layers for high-resolution AMOLED backplane",

abstract = "We developed a novel vertically integrated, double stack oxide thin-film transistor (TFT) backplane for high resolution organic light-emitting diode (OLED) displays. The 1st TFT layer is bulk-accumulation mode and 2nd TFT layer is a single gate with back-channel etched structure. The extracted mobilities and threshold voltages are higher than 10 cm2/Vs and 0~1V, respectively. Both TFTs are found to be extremely stable under the bias and temperature stress. The gate driver with width of 530 µm and a pitch of 18.6 µm was developed exhibiting well shifted signal up to the last stage of 900-stages without output degradation, which could be used for 1360ppi, TFT backplane.",

keywords = "Double stack structures, High definition, High resolution, Oxide, Thin-film transistor (TFT)",

author = "Suhui Lee and Yuanfeng Chen and Jeonggi Kim and Jin Jang",

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doi = "10.1002/sdtp.14019",

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T1 - Vertically integrated, double-stack oxide-TFT layers for high-resolution AMOLED backplane

AU - Lee, Suhui

AU - Chen, Yuanfeng

AU - Kim, Jeonggi

AU - Jang, Jin

PY - 2020

Y1 - 2020

N2 - We developed a novel vertically integrated, double stack oxide thin-film transistor (TFT) backplane for high resolution organic light-emitting diode (OLED) displays. The 1st TFT layer is bulk-accumulation mode and 2nd TFT layer is a single gate with back-channel etched structure. The extracted mobilities and threshold voltages are higher than 10 cm2/Vs and 0~1V, respectively. Both TFTs are found to be extremely stable under the bias and temperature stress. The gate driver with width of 530 µm and a pitch of 18.6 µm was developed exhibiting well shifted signal up to the last stage of 900-stages without output degradation, which could be used for 1360ppi, TFT backplane.

AB - We developed a novel vertically integrated, double stack oxide thin-film transistor (TFT) backplane for high resolution organic light-emitting diode (OLED) displays. The 1st TFT layer is bulk-accumulation mode and 2nd TFT layer is a single gate with back-channel etched structure. The extracted mobilities and threshold voltages are higher than 10 cm2/Vs and 0~1V, respectively. Both TFTs are found to be extremely stable under the bias and temperature stress. The gate driver with width of 530 µm and a pitch of 18.6 µm was developed exhibiting well shifted signal up to the last stage of 900-stages without output degradation, which could be used for 1360ppi, TFT backplane.

KW - Double stack structures

KW - High definition

KW - High resolution

KW - Oxide

KW - Thin-film transistor (TFT)

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DO - 10.1002/sdtp.14019

M3 - Conference article

AN - SCOPUS:85094196614

SN - 0097-966X

VL - 51

SP - 913

EP - 916

JO - Digest of Technical Papers - SID International Symposium

JF - Digest of Technical Papers - SID International Symposium

IS - 1

T2 - 57th SID International Symposium, Seminar and Exhibition, Display Week, 2020

Y2 - 3 August 2020 through 7 August 2020

ER -

Vertically integrated, double-stack oxide-TFT layers for high-resolution AMOLED backplane

Abstract

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Keywords

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